Semiconductor device and method of driving the same

ABSTRACT

To provide a semiconductor device and a driving method of the same that is capable of enlarging a signal amplitude value as well as increasing a range in which a linear input/output relationship operates while preventing a signal writing-in time from becoming long. The semiconductor device having an amplifying transistor and a biasing transistor and the driving method thereof, wherein an electric discharging transistor is provided and pre-discharge is performed.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and adriving method thereof. Specifically, the present invention relates toan MOS sensor device that has an image sensor function and to a drivingmethod of the same.

[0003] 2. Description of the Related Art

[0004] In recent years, the use of information equipment such as apersonal computer has spread widely, and hence the demand to read(store) various information in the personal computer, etc. as electronicinformation is rising. Therefore, replacing the conventional silver saltcamera, a digital still camera or a scanner, which is used as a means ofreading information printed on paper, are in the spotlight.

[0005] An area sensor in which the pixels are arranged in atwo-dimensional way is used in the digital still camera. In the scanner,a copier machine, etc., a line sensor in which the pixels are arrangedin a one-dimensional way is used. In the case of using the line sensorto read a two-dimensional image, signals are read while moving the linesensor.

[0006] A CCD type sensor is mainly used as the image sensor in thesetypes of image reading equipments. In the CCD type sensor, aphotoelectric conversion is carried out in a photo diode of each of thepixels and then the CCD is used to read those signals. However, an MOStype sensor that is formed by using a single crystal silicon substrateis showing signs of popularization in a part of the technical fieldthereof by using factors such as the incorporation of a peripheralcircuit, manufacturing it into one chip, its suitability for a real timesignal process, and its low consumption power as weapons. Further, themanufacture of an MOS type sensor by using a TFT that is formed on aglass substrate is being developed at the research level. In the MOStype sensor, the photoelectric conversion is carried out in the photodiode of each of the pixels, whereby the signals of the respectivepixels are read out by using a switch that is formed by an MOStransistor.

[0007] As a pixel structure of the MOS type sensor, various types arebeing developed. The various types of pixel structure of the MOS typesensor can be largely categorized into two types, that is, a passivesensor type and an active sensor type. The passive sensor is a sensor inwhich a signal amplitude element is not incorporated into the respectivepixels whereas the active sensor is a sensor in which a signal amplitudeelement is incorporated into the respective pixels. The active sensorhas an advantage over the passive sensor in that it is strong againstnoise because the signals are amplified in each of the pixels.

[0008] Shown in FIG. 2 is an example of a circuit of a pixel in thepassive sensor. A pixel 10005 is composed of a switching transistor10001 and a photo diode 10004. The photo diode is connected to a powersource standard line 10006 and to a source terminal of the switchingtransistor 10001. A gate signal line 10002 is connected to a gateterminal of the switching transistor 10001, and a signal output line10003 is connected to a drain terminal thereof. Photoelectric conversiontakes place in the photo diode 10004. In other words, an electric chargeis generated in response to the incidence of light, whereby the electriccharges are accumulated therein. Then the switching transistor 10001 ismade into conductive by controlling the gate signal line 10003 tothereby read out the electric charge of the photo diode 10004 throughthe signal output line 10003.

[0009] There are various kinds of pixel structure of the active sensor.Pixel structures such as a photo diode type and a photo gate type andtheir operations are introduced in IEDM95: p.17: CMOS Image Sensors,Electric Camera On a Chip or in IEDM97: p.201: CMOS Image Sensors—RecentAdvances and Device Scaling Considerations. In the ISSCC97: p.180: A ¼Inch 330k Square Pixel Progressive Scan CMOS Active Pixel Image Sensor,the pixel structure is categorized from the perspective of a selectingmethod of the pixel. That is, a case of whether to use a transistor or acapacitance as a selecting element is described therein. Thus, there arevarious types of structures regarding the number of transistors forforming one pixel. A general description of the CMOS type sensor isbroadly introduced in the JIEC Seminar: Development Prospects of theCMOS Camera: Feb. 20, 1998. In the description thereof, a logarithmconversion form, which outputs a signal of the logarithm of lightdensity by connecting a gate electrode and a drain electrode of aresetting transistor, is also explained.

[0010] As shown in FIG. 3, a pixel structure of the active sensor thatis mostly adopted is a type that is composed of three N channeltransistors and one photo diode, thereby forming one pixel 308. A Pchannel side terminal of a photo diode 304 is connected to a powersource standard line 312, and an N channel side terminal of the photodiode 304 is connected to a gate terminal of an amplifying transistor306. A drain terminal and a source terminal of the amplifying transistor306 are connected to a power source line 309 and to a drain terminal ofa switching transistor 301, respectively. A gate terminal of theswitching transistor 301 is connected to a gate signal line 302 while asource terminal thereof is connected to a signal output line 303. A gateterminal of a resetting transistor 307 is connected to a reset signalline 306. A source terminal and a drain terminal of the resettingtransistor 306 are connected to the power source line 309 and a gateterminal of the amplifying transistor 306, respectively.

[0011] In the case of an area sensor, not only one pixel 308 isconnected to one signal output line 303, but also a plurality of pixelsare connected thereto. However, one biasing transistor 311 is connectedper signal output line 303. Agate terminal of the biasing transistor 311is connected to a bias signal line 310. A source terminal and a drainterminal of the biasing transistor 311 are connected to the signaloutput line 303 and to a biasing power source line 313.

[0012] Next, a basic operation of the pixel 308 will be explained.

[0013] The resetting transistor 307 is first made into a conductivestate. Because the P channel side terminal of the photo diode 304 isconnected to the power source standard line 312, whereby the photo diode304 becomes a state in which the N channel side terminal is electricallyconnected to the power source line 309, an inverted bias voltage isapplied to the photo diode 304. Hereinafter, the operation of chargingthe N channel side terminal of the photo diode 304 until its electricpotential is equivalent to the electric potential of the power sourceline 309 will be referred as “reset”. Thereafter, the resettingtransistor 307 is made into a non-conductive state. When light is beingirradiated to the photo diode 304, an electric charge is generated dueto a photoelectric conversion. Therefore, as time elapses, the electricpotential of the N channel side terminal of the photo diode 304, whichhas been charged up to the electric potential of the power source line309, gradually becomes smaller because of an electric charge that wasgenerated by the light. Then after a fixed period of time has passed,the switching transistor 301 is made into a conductive state, whereby asignal is outputted to the signal output line 303 through the amplifyingtransistor 306.

[0014] However, at the time the signal is being outputted, an electricpotential is applied to the bias signal line 310 to cause a current toflow in the biasing transistor 311. Therefore, the amplifying transistor306 and the biasing transistor 311 operate as the so-called sourcefollower circuits.

[0015] An example of the most basic source follower circuit is shown inFIG. 4. In FIG. 4, the case of using the N channel transistor isdescribed. Although a P channel transistor can be used to construct thesource follower circuit, a case of using an N channel transistor isshown in FIG. 4. A power source electric potential Vdd is applied to anamplifier side power source line 403. A standard electric potential 0 Vis applied to a bias side power source line 404. A drain terminal of anamplifying transistor 401 is connected to the amplifier side powersource line 403 while a source terminal thereof is connected to a drainterminal of a biasing transistor 402. A source terminal of the biasingtransistor 402 is connected to the bias side power source line 404. Abias electric potential Vb is applied to a gate terminal of the biasingtransistor 402. Therefore, a bias current Ib flows in the biasingtransistor 402. The biasing transistor 402 basically operates as a fixedelectric current source. A gate terminal of the amplifying transistor401 serves as an input terminal 406. An input electric potential Vin isthus applied to the gate terminal of the amplifying transistor 401. Asource terminal of the amplifying transistor 401 serves as an outputterminal 407, and therefore an output electric potential Vout is appliedto the source terminal of the amplifying transistor 401. At this point,the relationship of the input/output of the source follower circuitbecomes Vout=Vin−Vb.

[0016] In the case of comparing the circuit configurations of FIG. 3 andFIG. 4, the amplifying transistor 306 corresponds to the amplifyingtransistor 401, and the biasing transistor 311 corresponds to thebiasing transistor 402. Because it is assumed that the switchingtransistor 301 is in conductive, it can be observed that a switchingtransistor is omitted in FIG. 4. The electric potential of the N channelside terminal of the photo diode 304 corresponds to the input electricpotential Vin (the gate electric potential of the amplifying transistor401, that is, the electric potential of the input terminal 406). Theelectric potential of the signal output line 303 corresponds to theoutput electric potential Vout (the source electric potential of theamplifying transistor 401, that is, the electric potential of the outputterminal 407).

[0017] Therefore, in FIG. 3, if the electric potential of the N channelside terminal of the photo diode 304 is Vpd, the electric potential ofthe bias signal line 310, that is, the bias electric potential is Vb,the electric potential of the signal output line 303 is Vout, and theelectric potential of the power source standard line 312 and the biasside power source line 313 is 0 V, then the relationship becomesVout=Vpd−Vb. Accordingly, when the electric potential Vpd of the Nchannel side terminal of the photo diode 304 changes, then Vout alsochanges. As a result, the change of the Vpd can be outputted as a signaland the light intensity can thus be read.

[0018] The basic operation of the source follower circuit is one asdescribed above. However, the operating principle of the source followercircuit will be explained next in detail because it is needed forexplaining the operation of the present invention. For simplification,it is assumed that the sizes and characteristics of the amplifyingtransistor and the biasing transistor are the same in the explanationhere. Further, an electric current characteristic of the transistors isan ideal one, that is, even if a voltage between the source and thedrain changes, it is assumed that an electric current value in asaturated region does not change.

[0019] First, as shown in FIG. 4, the bias electric potential Vb isapplied to the gate terminal of the biasing transistor 402. In the casethe biasing transistor 402 operates in the saturated region, theelectric current Ib flows therein as shown in FIG. 5. On the other hand,the same amount of electric current will flow in amplifying transistor401 and the biasing transistor 402 under a fixed normal state becauseboth transistors are connected in series. Therefore, when the electriccurrent Ib is flowing in the biasing transistor 402, the electriccurrent Ib is also flowing in the amplifying transistor 401. In order tocause the electric current Ib to flow in the amplifying transistor 401,it is necessary to make the voltage Vgs between the gate and the sourceof the amplifying transistor 401 equivalent to the bias electricpotential Vb.

[0020] Thus, the output electric potential Vout in the source followercircuit is obtained. The amount of electric potential of the outputelectric potential Vout that is lower than the input electric potentialVin is equal to only that of the voltage Vgs between the gate and thesource of the amplifying transistor 401. Therefore, the input/outputrelationship becomes Vout=Vin−Vgs. The voltage Vgs between the gate andthe source of the amplifying transistor 401 is equal to the biaselectric potential Vb, and hence the input/output relationship becomesVout=Vin−Vb. However, as shown in FIG. 5, this equation is only validwhen the biasing transistor 402 operates in the saturated region(corresponds to the case when Vin is large). In the case Vin is smalland the biasing transistor 402 operates in a linear region, the equationVout=Vin−Vb cannot become valid as shown in FIG. 6. When the biasingtransistor operates in the linear region, the input/output relationshipbecomes Vout=Vin−Vb′. The Vb′ here is the voltage between the gate andthe source of the amplifying transistor 401 at that point. If theelectric current flowing in the biasing transistor 402 is Ib′ when thebiasing transistor 402 is operating in the linear region, then Ib′<Ib.Consequently, the relationship between Vb and Vb′ becomes Vb′<Vb. Inother words, when Vin and Ib′ becomes small, then Vb′ also becomessmall. As a result, the input/output relationship (relationship betweenVin and Vout) becomes non-linear as shown in FIG. 7.

[0021] The following fact can be discerned from the above explanation.

[0022] First, to increase an amplitude value of the output electricpotential Vout in the source follower circuit, it is appropriate to makethe bias electric potential Vb small. Since Vout=Vin−Vb, when Vb issmall, the Vout can be increased. However, it is necessary that thebiasing transistor 402 be in conductive. Therefore, the value of thebias electric potential Vb must be made larger than that of a thresholdvoltage of the biasing transistor 402.

[0023] To the contrary, in the case the bias electric potential Vb islarge, the biasing transistor 402 can readily operate in the linearregion when the input electric potential Vin becomes small. As a result,the input/output relationship of the source follower circuit is likelyto become non-linear. It is appropriate, in this respect, to make thebias electric potential Vb small.

[0024] The operation of the source follower circuit under a fixed normalstate has been explained so far. Next, the operation of the sourcefollower circuit under a transient state will be explained. As a circuitstructure thereof, the circuit shown in FIG. 4 will be used with theaddition of a load. In other words, the circuit structure here is astructure in which a load capacitance 805 is connected between outputterminals, that is, a source terminal of an amplifying transistor 801and a load capacitance power source line 806 as shown in FIG. 8.Therefore, the electric potential of the load capacitance 805 is thesame as the output electric potential Vout of the source followercircuit.

[0025] First, a case where the output electric potential Vout is smallin the initial state, that is, when Vout<Vin−Vb. FIG. 8A is a diagramshowing a circuit configuration, and FIG. 8B is a diagram showing atiming chart. In that case, a value of a voltage Vgs between a gate anda source of an amplifying transistor 801 is larger than a value of avoltage Vgs between a gate and a source of a biasing transistor 802.Therefore, a large electric current flows in the amplifying transistor801, and as a result, a load capacitance 805 is rapidly charged and theoutput electric potential Vout becomes large, whereby the voltage Vgsbetween the gate and the source of the amplifying transistor 801 becomessmaller. When the voltage Vgs between the gate and the source of theamplifying transistor 801 finally becomes equivalent to the biaselectric potential Vb, the transient state is turned into a fixed normalstate. The output electric potential Vout at that point isVout=Vin−Vgs=Vin−Vb. Thus, as in the case where Vout<Vin−Vb, initiallythe voltage Vgs between the gate and the source of the amplifyingtransistor 801 is large under the transient state. Therefore, a largeelectric current, passing through the amplifying transistor 801, flowsto the load capacitance 805. The writing-in time of a signal to the loadcapacitance 805 can thus be performed in a short time.

[0026] On the other hand, a case is discussed where the output electricpotential Vout is large in the initial state, that is, when Vout>Vin−Vb.FIG. 9A is a diagram showing a circuit configuration thereof, and FIG.9B is a diagram showing a timing chart thereof. In that case, because avalue of a voltage Vgs between a gate and a source of an amplifyingtransistor 901 is small, the amplifying transistor 901 is in anon-conductive state. Then, the electric charges that have accumulatedin a load capacitance 905 flow through a biasing transistor 902 tothereby be discharged. At that point, a voltage between a gate and asource of the biasing transistor 902 is the bias electric potential Vb,and therefore the electric current flowing in the biasing transistor 902becomes Ib. As the output electric potential Vout gradually becomessmaller, the voltage Vgs between the gate and the source of theamplifying transistor 901 becomes larger. When the voltage Vgs betweenthe gate and the source of the amplifying transistor 901 finally becomesequivalent to the bias electric potential Vb, the transient state isturned into the fixed normal state. Under the fixed normal state, thevalue of Vout is a fixed value, and hence an electric current will notflow in the load capacitance 905. The electric current Ib willcontinuously flow in the 2 transistors of the source follower circuit.

[0027] Thus, from the above explanation, it can be understood that whenVout>Vin−Vb, the electric discharging time of the load capacitance 905,that is, the signal writing-in time is determined by the electriccurrent Ib flowing through the biasing transistor 902. The amount of theelectric current Ib is determined by the size of the bias electricpotential Vb. Therefore, to increase the electric current in order toshorten the signal writing-in time to the load capacitance 905, it isnecessary to increase the bias electric potential Vb.

[0028] Next, a timing chart of a signal in a pixel 309 is shown in FIG.10. First, the resetting transistor 307 is turned into a conductivestate by controlling the reset signal line 305, whereby the electricpotential of the N channel side terminal of the photo diode 304 ischarged until the electric potential Vd of the power source line 309. Inother words, the pixel is reset. Subsequently, the resetting transistor307 is turned into a non-conductive state by controlling the resetsignal line 305. Thereafter, when light is irradiated to the photo diode304, an electric charge according to the light density is generated.Therefore, the electric charge that is charged due to the resettingoperation is gradually being discharged. In short, the electricpotential of the N channel side terminal of the photo diode 304decreases. In the case a dark light is irradiated to the photo diode304, the amount of electric discharge is small, and therefore theelectric potential of the N channel side terminal of the photo diode 304does not decrease much. Then, at a certain point, the switchingtransistor 301 is turned into a conductive state to thereby read-out theelectric potential of the N channel side terminal of the photo diode 304as a signal. This signal is proportional to the density of light. Then,the resetting transistor 307 is turned into the conductive state againto thereby reset the photo diode 304, and similar operations arerepeated.

[0029] A transistor in the pixel 309 will be explained next. Regardingthe polarity of the transistor thereof, all are N channel types most ofthe time. In rare cases, a P channel type may be used for the resettingtransistor (JIEC Seminar: Development Prospects of the CMOS Camera: Feb.20, 1998, refer to FIG. 11). Further, with regard to a method of liningup (arranging) the amplifying transistor and a selecting transistor, Nchannel types are used for both transistors and as shown in FIG. 3,often the structure is one in which the power source line 309 and theamplifying transistor 306 are connected, the amplifying transistor 306and the switching transistor 301 are connected, and the switchingtransistor 301 and the signal output line 303 are connected. In rarecases N channel types are used for both transistors and the structurethereof is one in which the power source line 309 and the switchingtransistor 301 are connected, the switching transistor 301 and theamplifying transistor 306 are connected, and the amplifying transistor306 and the signal output line 306 are connected (ISSCC97: p.180, A ¼Inch 330K Square Pixel Progressive Scan CMOS Active Pixel Image Sensor).

[0030] Next, a sensor portion for performing photoelectric conversion orthe like will be explained. A PN type of photo diode is usually used toconvert light into electricity. However, there are other types includinga PIN type diode, an avalanche diode, an NPN incorporated diode, aSchottky diode, etc. There are also others such as a photo diode forX-rays and a sensor for infrared rays. These are described in “TheBasics of Solid Imaging Elements: DENSHINO MENO SHIKUMI” written byTakao Ando and Hirohito Kobuchi: Nippon Riko Shuppan Kai.

[0031] Products suitable as sensors will be explained next. Other thanthe digital still camera and scanner, a sensor may also be used in anX-ray camera. In that case, there is a case where the photo diode fordirectly converting an X-ray into an electric signal is used or a casewhere an X-ray is converted into light by using a fluorescent materialor a scintillator and then the light is read. The case of converting anX-ray into light by using a scintillator and thereafter reading thelight is described in “Euro Display 99: p.203: X-ray Detectors base onAmorphous Silicon Active Matrix”. In the “IEDM 98: p.21: AmorphousSilicon TFT X-ray Image Sensors”, a case of reading light by using anamorphous silicon is reported, and a case of reading light by using aphoto conductor is reported in the “AM-LCD99: p.45: Real-time ImagingFlat Panel X-ray Detector”.

[0032] First, consideration is made on the item required in a sourcefollower circuit 405. The most necessary item is to obtain a value aslarge as possible as an amplitude of the output electric potential Vout,that is, a value that is roughly equivalent to an amplitude of the inputelectric potential Vin. If the amplitude of the output electricpotential Vout is large, signals having a large number of gradations canbe obtained. As a result, the quality of the image read from an imagesensor is enhanced. In addition, it is necessary that the input/outputrelationship is linear. In other words, it is crucial that therelationship of the input electric potential Vin and the output electricpotential Vout in the source follower circuit operate linearly in a widerange. That is, the relationship of Vout=Vin−Vb is maintained even ifthe input electric potential Vin is small. In short, it is importantthat the biasing transistor 402 operate in the saturated region. Otheritems that are necessary include a short signal writing-in time of theoutput electric potential Vout to the load capacitance. If the signalwriting-in time is long, the operation thereof will become slow.

[0033] Then, consideration is now made regarding a method to satisfy theabove-mentioned items required in the source follower circuit.

[0034] First, because Vout=Vin−Vb, it is appropriate to make the biaselectric potential Vb small in order to increase the amplitude of theoutput electric potential Vout. Similarly, the bias electric potentialVb may be made small in order to widen the operating region of a linearinput/output relationship. The reason for this resides in that when thebias electric potential Vb is small, the biasing transistor 402 caneasily operate in the saturated region even if the output electricpotential has become small. However, when the bias electric potential Vbis small, the writing-in time of the output signal becomes long.

[0035] In other words, the amplitude of the output electric potentialand the signal writing-in time have a trade-off relationship. It isimpossible to shorten the writing-in time of the output electricpotential while increasing the amplitude value of the output electricpotential. In addition, it is also impossible to widen the operatingregion in which the input/output relationship is linear while increasingthe amplitude value of the output electric potential.

SUMMARY OF THE INVENTION

[0036] The present invention has been made in view of the aboveproblems, and therefore has an object to solve the above problems of theprior art.

[0037] According to the present invention, in a source follower circuitthat employs an N channel transistor, prior to outputting a signaltherefrom, an output electric potential (electric potential of a loadcapacitance) is lowered once (in the case of a source follower circuitemploying a P channel transistor, the output electric potential israised). Hereinafter, the process of lowering the output electricpotential (electric potential of the load capacitance) of the sourcefollower circuit (in the case where a P channel is employed, increasingthe electric potential thereof) is referred to as “pre-discharge”, and aperiod during which the pre-discharge is performed is referred to as“pre-discharge period”. In the present invention, an actual signal isoutputted after a pre-discharge.

[0038] Conventionally, in a source follower circuit employing an Nchannel transistor, an electric charge of the load capacitance wasdischarged through a biasing transistor when Vout>Vin−Vb in the initialstate. However, in the present invention, the electric potential of theload capacitance is lowered once to thereby make the source followercircuit in a state where Vout<Vin−Vb. This operation is thepre-discharge. Thereafter, the actual signal is outputted. Since thefollower circuit is already in the state where Vout<Vin−Vb at the timeof outputting the actual signal, the signal is outputted to the loadcapacitance through an amplifying transistor. Therefore, the signalwriting-in time does not become long.

[0039] An electric potential that is slightly higher than a thresholdvoltage of the biasing transistor, that is, an electric potential valueas low as possible, is applied to a gate electric potential of thebiasing transistor when outputting the actual signal, in other words,the bias electric potential Vb. The reasons for this resides in thatconsidering the input/output relationship Vout=Vin−Vb of the sourcefollower circuit, it is preferable to lower the bias electric potentialVb as much as possible in order to increase the output electricpotential Vout. However, it is necessary that the biasing transistor bein conductive state. In short, it is necessary that the biasingtransistor operate in the saturated region. Accordingly, the gateelectric potential of the biasing transistor when outputting the actualsignal, that is, the bias electric potential Vb is made slightly higherthan the threshold voltage of the biasing transistor. In practice, theelectric potential is made slightly higher than the highest thresholdvoltage in all the biasing transistors in a circuit.

[0040] Even if, the bias electric potential Vb is made small, andtherefore the amount of electric current of the biasing transistorbecomes small, the electric charge of the load capacitance is notdischarged through the biasing transistor. Hence, the signal writing-intime does not become long. In addition, because the bias electricpotential is small, the operating region in which the input/outputrelationship is linear is wide. Therefore, it is possible to prevent thesignal writing-in time from becoming long, and enlarging the amplitudeof the output electric potential and widening the operating region inwhich the input/output relationship is linear at the same time. Thestructure of the present invention will be described below.

[0041] According to the present invention, there is provided asemiconductor device having an amplifying transistor, a biasingtransistor, an amplifying side power source line, a biasing side powersource line, a bias signal line, an electric discharging transistor, andan electric discharging power source line, characterized in that:

[0042] a drain terminal of the amplifying transistor is connected to theamplifying side power source line, a source terminal of the biasingtransistor is connected to the biasing side power source line, a sourceterminal of the amplifying transistor is connected to a drain terminalof the biasing transistor, a gate terminal of the biasing transistor isconnected to the bias signal line, a gate terminal of the amplifyingtransistor serves as an input terminal, and a source terminal of theamplifying transistor serves as an output terminal, and

[0043] one of the output terminal and the electric discharging powersource line is connected to a source terminal of the electricdischarging transistor while the other thereof is connected to a drainterminal of the electric discharging transistor.

[0044] According to the present invention, there is provided asemiconductor device having an amplifying transistor, a biasingtransistor, an amplifying side power source line, a biasing side powersource line, and a bias signal line, characterized in that:

[0045] a drain terminal of the amplifying transistor is connected to theamplifying side power source line, a source terminal of the biasingtransistor is connected to the biasing side power source line, a sourceterminal of the amplifying transistor is connected to a drain terminalof the biasing transistor, a gate terminal of the biasing transistor isconnected to the bias signal line, a gate terminal of the amplifyingtransistor serves as an input terminal, and a source terminal of theamplifying transistor serves as an output terminal, and

[0046] a signal generating device is connected to the bias signal linefor performing the operation of making the electric potential of thebiasing side power source line close to the electric potential of theamplifying side power source line.

[0047] According to the present invention, there is provided asemiconductor device, characterized in that one terminal of a loadcapacitance is connected to the output terminal, and the other terminalof the load capacitance is connected to a load capacitance power sourceline.

[0048] According to the present invention, there is provided asemiconductor device, characterized in that the electric dischargingpower source line is connected to the biasing side power source line.

[0049] According to the present invention, there is provided asemiconductor device, characterized in that at least 2 lines from amongthe electric discharging power source line, the load capacitance powersource line, and the biasing side power source line are connectedtogether.

[0050] According to the present invention, there is provided asemiconductor device, characterized in that the load capacitance powersource line is connected to the amplifying side power source line.

[0051] According to the present invention, there is provided asemiconductor device, characterized in that the semiconductor device hasat least one selecting switch for controlling an electric currentflowing to the load capacitance or the output terminal from theamplifying side power source line or from the biasing side power sourceline.

[0052] According to the present invention, there is provided asemiconductor device, characterized in that the semiconductor device hasat least one selecting switch for controlling an electric currentflowing to the output terminal from the amplifying side power sourceline or from the biasing side power source line.

[0053] According to the present invention, there is provided asemiconductor device, characterized in that the selecting switch has atleast one of an N channel transistor or a P channel transistor.

[0054] According to the present invention, there is provided asemiconductor device, characterized in that an absolute value of avoltage between a gate and a source of the biasing transistor isequivalent to a minimum value of an absolute value of a voltage betweena gate and a source that is necessary for making the biasing transistorinto a conductive state.

[0055] According to the present invention, there is provided asemiconductor device, characterized in that a photoelectric conversionelement is connected to the input terminal.

[0056] According to the present invention, there is provided asemiconductor device, characterized in that a signal generated by aphotoelectric conversion element is fed to the input terminal.

[0057] According to the present invention, there is provided asemiconductor device, characterized in that the photoelectric conversionelement is either an X-ray sensor or an infrared sensor.

[0058] According to the present invention, there is provided asemiconductor device, characterized in that the photoelectric conversionelement is any one of a photo diode, a Schottky diode, an avalanchediode, or a photo conductor.

[0059] According to the present invention, there is provided asemiconductor device, characterized in that the photo diode is one of atype incorporating a PN type, a PIN type, or an NPN embedded type.

[0060] According to the present invention, there is provided asemiconductor device, characterized in that the semiconductor device hasa resetting transistor, and a source terminal or a drain terminal of theresetting transistor is connected to the photoelectric conversionelement.

[0061] According to the present invention, there is provided asemiconductor device, characterized in that when the semiconductordevice has a plurality of biasing transistors, an absolute value of avoltage between a gate and a source of the plurality of biasingtransistors is equivalent to a minimum value of an absolute value of avoltage between a gate and a source that is necessary for making theentire plurality of biasing transistors into a conductive state.

[0062] According to the present invention, there is provided asemiconductor device, characterized in that the amplifying transistor,the biasing transistor, and the electric discharging transistor aretransistors having the same polarity.

[0063] According to the present invention, there is provided a drivingmethod of a semiconductor device having an amplifying transistor, abiasing transistor, an amplifying side power source line, a biasing sidepower source line, and a bias signal line, characterized in that:

[0064] a drain terminal of the amplifying transistor is connected to theamplifying side power source line, a source terminal of the biasingtransistor is connected to the biasing side power source line, a sourceterminal of the amplifying transistor is connected to a drain terminalof the biasing transistor,

[0065] a gate terminal of the biasing transistor is connected to thebias signal line, a gate terminal of the amplifying transistor serves asan input terminal, and a source terminal of the amplifying transistorserves as an output terminal, and characterized in that

[0066] the driving method outputs a signal after performing apre-discharge.

[0067] According to the present invention, there is provided a drivingmethod of a semiconductor device having an amplifying transistor, abiasing transistor, an amplifying side power source line, a biasing sidepower source line, and a bias signal line, characterized in that:

[0068] a drain terminal of the amplifying transistor is connected to theamplifying side power source line, a source terminal of the biasingtransistor is connected to the biasing side power source line, a sourceterminal of the amplifying transistor is connected to a drain terminalof the biasing transistor, a gate terminal of the biasing transistor isconnected to the bias signal line, a gate terminal of the amplifyingtransistor serves as an input terminal, and a source terminal of theamplifying transistor serves as an output terminal, and characterized inthat

[0069] the driving method outputs a signal after performing apre-discharge by making an electric potential of the biasing side powersource line close to an electric potential of the amplifying side powersource line.

[0070] According to the present invention, there is provided a drivingmethod of a semiconductor device having an amplifying transistor, abiasing transistor, an amplifying side power source line, a biasing sidepower source line, and a bias signal line, an electric dischargingtransistor, and an electric discharging power source line characterizedin that:

[0071] a drain terminal of the amplifying transistor is connected to theamplifying side power source line, a source terminal of the biasingtransistor is connected to the biasing side power source line, a sourceterminal of the amplifying transistor is connected to a drain terminalof the biasing transistor, a gate terminal of the biasing transistor isconnected to the bias signal line, a gate terminal of the amplifyingtransistor serves as an input terminal, a source terminal of theamplifying transistor serves as an output terminal, one of the outputterminal and the electric discharging power source line is connected toa source terminal of the electric discharging transistor while the otherthereof is connected to a drain terminal of the electric dischargingtransistor, and characterized in that the driving method outputs asignal after performing a pre-discharge by making the electricdischarging transistor into a conductive state.

[0072] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that a value of anelectric potential of the electric discharging power source line takes avalue that is between an electric potential of the bias signal line andan electric potential of the biasing side power source line.

[0073] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that one terminal ofa load capacitance is connected to the output terminal, and the otherterminal of the load capacitance is connected to a load capacitancepower source line.

[0074] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that the electricdischarging power source line and the biasing side power source line areto be connected together.

[0075] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that at least 2 linesfrom among the electric discharging power source line, the loadcapacitance power source line, and the biasing side power source lineare to be connected together.

[0076] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that the loadcapacitance power source line is connected to the amplifying side powersource line.

[0077] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that the drivingmethod of a semiconductor device has at least one selecting switch forcontrolling an electric current flowing to the load capacitance or theoutput terminal from the amplifying side power source line or from thebiasing side power source line.

[0078] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that the drivingmethod of a semiconductor device has at least one selecting switch forcontrolling an electric current flowing to the output terminal from theamplifying side power source line or from the biasing side power sourceline.

[0079] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that the selectingswitch has at least one of an N channel transistor or a P channeltransistor.

[0080] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that an absolutevalue of a voltage between agate and a source of the biasing transistoris equivalent to a minimum value of an absolute value of a voltagebetween a gate and a source that is necessary for making the biasingtransistor into a conductive state.

[0081] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that a photoelectricconversion element is connected to the input terminal.

[0082] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that a signalgenerated by a photoelectric conversion element is fed to the inputterminal.

[0083] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that thephotoelectric conversion element is either an X-ray sensor or aninfrared sensor.

[0084] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that thephotoelectric conversion element is any one of a photo diode, a Schottkydiode, an avalanche diode, or a photo conductor.

[0085] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that the photo diodeis any one of a type incorporating a PN type, a PIN type, or an NPNembedded type.

[0086] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that the drivingmethod of a semiconductor device has a resetting transistor, and theresetting transistor resets the photoelectric conversion element.

[0087] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that when the drivingmethod of a semiconductor device has a plurality of biasing transistors,an absolute value of a voltage between a gate and a source of theplurality of biasing transistor is equivalent to a minimum value of anabsolute value of a voltage between a gate and a source that isnecessary for making the entire plurality of biasing transistors into aconductive state.

[0088] According to the present invention, there is provided a drivingmethod of a semiconductor device, characterized in that the amplifyingtransistor, the biasing transistor, and the electric dischargingtransistor are transistors having the same polarity.

BRIEF DESCRIPTION OF THE DRAWINGS

[0089] The above and other objects and features of the present inventionwill be more apparent from the following description taken inconjunction with the accompanying drawings:

[0090]FIGS. 1A and 1B are diagrams showing a circuit configuration and atiming chart, respectively, of a source follower circuit of the presentinvention;

[0091]FIG. 2 is a diagram showing a circuit configuration of a pixel ofa conventional passive sensor;

[0092]FIG. 3 is a diagram showing a circuit configuration of a pixel ofa conventional active sensor;

[0093]FIG. 4 is a diagram showing a circuit configuration of aconventional source follower circuit;

[0094]FIG. 5 is a diagram showing an electric current characteristic ofa source follower circuit;

[0095]FIG. 6 is a diagram showing an electric current characteristic ofa source follower circuit;

[0096]FIG. 7 is a diagram showing an input/output characteristic of asource follower circuit;

[0097]FIGS. 8A and 8B are diagrams showing a circuit configuration and atiming chart, respectively, of a source follower circuit;

[0098]FIGS. 9A and 9B are diagrams showing a circuit configuration and atiming chart, respectively, of a source follower circuit;

[0099]FIG. 10 is a diagram showing a timing chart of an active sensor;

[0100]FIGS. 11A and 11B are diagrams showing a circuit configuration anda timing chart, respectively, of a source follower circuit of thepresent invention;

[0101]FIGS. 12A and 12B are diagrams showing a circuit configuration anda timing chart, respectively, of a source follower circuit of thepresent invention;

[0102]FIGS. 13A and 13B are diagrams showing a circuit configuration anda timing chart, respectively, of a source follower circuit of thepresent invention;

[0103]FIGS. 14A and 14B are diagrams showing a circuit configuration anda timing chart, respectively, of a source follower circuit of thepresent invention;

[0104]FIGS. 15A and 15B are diagrams showing a circuit configuration anda timing chart, respectively, of a source follower circuit of thepresent invention;

[0105]FIGS. 16A and 16B are diagrams showing a circuit configuration anda timing chart, respectively, of a source follower circuit of thepresent invention;

[0106]FIGS. 17A and 17B are diagrams showing a circuit configuration anda timing chart, respectively, of a source follower circuit of thepresent invention;

[0107]FIGS. 18A and 18B are diagrams showing a circuit configuration anda timing chart, respectively, of a source follower circuit of thepresent invention;

[0108]FIGS. 19A and 19B are diagrams showing a circuit configuration anda timing chart, respectively, of a source follower circuit of thepresent invention;

[0109]FIG. 20 is a block diagram of an area sensor of the presentinvention;

[0110]FIG. 21 is a diagram showing a circuit configuration of a pixel ofan active sensor of the present invention;

[0111]FIG. 22 is a diagram showing a circuit configuration of a pixel ofan active sensor of the present invention;

[0112]FIG. 23 is a diagram showing a circuit configuration of a signalprocessing circuit of the present invention;

[0113]FIG. 24 is a diagram showing a circuit configuration of a finaloutput amplifying circuit signal of the present invention;

[0114]FIG. 25 is a diagram showing a circuit configuration of a finaloutput amplifying circuit signal of the present invention;

[0115]FIG. 26 is a diagram showing a timing chart of an area sensor ofthe present invention;

[0116]FIG. 27 is a diagram showing a timing chart of an area sensor ofthe present invention;

[0117]FIG. 28 is a diagram showing a timing chart of an area sensor ofthe present invention;

[0118]FIG. 29 is a diagram showing a circuit configuration of a signalprocessing circuit of the present invention;

[0119]FIGS. 30A to 30D are diagrams showing manufacturing processes ofan image sensor of the present invention;

[0120]FIGS. 31A to 31D are diagrams showing manufacturing processes ofan image sensor of the present invention;

[0121]FIGS. 32A to 32C are diagrams showing manufacturing processes ofan image sensor of the present invention;

[0122]FIGS. 33A and 33B are diagrams showing manufacturing processes ofan image sensor of the present invention;

[0123]FIGS. 34A and 34B are diagrams showing electronic equipments usingthe image sensor of the present invention;

[0124]FIG. 35 is a diagram showing an electronic equipment using theimage sensor of the present invention;

[0125]FIG. 36 is a diagram showing an electronic equipment using theimage sensor of the present invent ion; and

[0126]FIG. 37 is a diagram showing an electronic equipment using theimage sensor of the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0127] Embodiment Mode 1

[0128] A typical embodiment mode of the present invention is shown inthe following.

[0129] Shown in FIGS. 11A and 11B is an example of a pre-dischargeimplementation method. FIG. 11A is a diagram showing a circuitconfiguration of the pre-discharge implementation method, and FIG. 11Bis a diagram showing a signal timing chart thereof. In FIGS. 11A and11B, pre-discharge is performed by arranging an exclusive electricdischarging transistor 1108. FIGS. 11A and 11B are diagrams illustratingan example of a case in which an N channel transistor is used toconstruct the source follower circuit.

[0130] An electric potential of a gate terminal of an amplifyingtransistor 1101 (input terminal 1105) becomes an input electricpotential Vin. This input electric potential Vin corresponds to anelectric potential of an N channel side terminal of a photo diode. Adrain terminal of the amplifying transistor 1101 is connected to anamplifying side power source line 1103, and a source terminal thereof isconnected to a drain terminal of a biasing transistor 1102. The sourceterminal of the amplifying transistor 1101 serves as an output terminal1107 and an electric potential thereof becomes an output electricpotential Vout. A bias electric potential Vb is applied to a gateterminal of the biasing transistor 1102. A source terminal of thebiasing transistor 1102 is connected to a biasing side power source line1104. A source terminal and a drain terminal of the electric dischargingtransistor 1108 are connected to the output terminal 1107 of the sourcefollower circuit (source terminal of the amplifying transistor 1101) andan electric discharging power source line 1109.

[0131] As shown in FIG. 11B, when the electric discharging transistor1108 is in conductive, the electric potential of the output terminal1107 becomes the electric potential of the electric discharging powersource line 1109 to thereby carry out pre-discharge. During apre-discharge period, a large electric current can be caused to flow tothe electric discharging transistor 1108 because the gate electricpotential of the electric discharging transistor 1108 is large. As aresult, the output electric potential Vout can be rapidly lowered,whereby the pre-discharge period is shortened. In this method, the biaselectric potential Vb may be equivalent to that of the prior art, or maybe large.

[0132] An actual signal is outputted after the pre-discharge. In thatcase, since the source follower circuit is in the Vout<Vin−Vb state, alarge electric current flows to the amplifying transistor 1101 as thevoltage between the gate and the source thereof is large. Consequently,a signal writing-in can be done in a short time.

[0133] Taking the input/output relationship of Vout=Vin−Vb intoconsideration, it is appropriate to make the bias electric potential Vbas low as possible when outputting the output electric potential Vout inorder to increase the output electric potential Vout. However, thebiasing transistor 1102 must be in conductive. In other words, thebiasing transistor 1102 must be operable in the saturated region and avalue in which a fixed electric current can flow therein. Therefore,other than during the pre-discharge period, an optimum value of anabsolute value of a bias signal electric potential (voltage between thegate and the source of the biasing transistor) is an electric potentialthat is slightly higher than an absolute value of a threshold voltage ofthe biasing transistor 1102.

[0134] Further, when the bias electric potential Vb is low, theoperating region in which the input/output relationship is linear can bewidened because the biasing transistor 1102 can readily operate in thesaturated region.

[0135] Thus, from the above consequences, it is possible to prevent thesignal writing-in time from becoming long, and enlarging the amplitudeof the output electric potential and widening the operating region inwhich the input/output relationship is linear can be realized at thesame time.

[0136] With regard to the polarity of the electric dischargingtransistor 1108, the polarity thereof may be similar to those of theamplifying transistor 1101 and the biasing transistor 1102, that is, inFIGS. 11A and 11B, an N channel type. The reason for this resides inthat when making the electric discharging transistor 1108 into aconductive, if an N channel type is used to form the electricdischarging transistor 1108, then the voltage between the gate and thesource thereof can large because the electric potential of the electricdischarging power source line 1109 is low. If the polarity of theelectric discharging transistor 1108 is different from that of theamplifying transistor 1101 and that of the biasing transistor 1102, thatis, in FIGS. 11A and 11B, if a P channel type is used to form theelectric discharging transistor 1108, it is necessary to apply anextremely low electric potential to the gate terminal of the electricdischarging transistor 1108. In other words, it is necessary to apply anelectric potential that is lower than the electric potential of thebiasing side power source line 1104. Therefore, from the aboveexplanation, it is desirable to make the polarity of the electricdischarging transistor 1108 similar to that of the amplifying transistor1101 and that of the biasing transistor 1102.

[0137] Note that in FIGS. 11A and 11B, a plurality of electricdischarging transistors 1108N may be used, in which case transistors ofboth polarities may be used.

[0138] Next, the electric potential of the electric discharging powersource line 1109 will be explained. To perform pre-discharge is to setthe state of the circuit to Vout<Vin−Vb. Therefore, the electricpotential of the electric discharging power source line 1109 has to beset to a low electric potential. The electric potential thereof may belower than the electric potential of the biasing side power source line1104. However, since the electric potential operation range of theoutput terminal 1107 is between the electric potential of the amplifyingside power source line 1103 and the electric potential of the biasingside power source line 1104. Even if the electric potential of theelectric discharging power source line 1109 is made lower than theelectric potential of the biasing side power source line 1104, noimprovement is obtained. In the case where the electric potential of theelectric discharging power source line 1109 is higher than the electricpotential of the biasing side power source line 1104, the state ofVout<Vin−Vb may not be attained if the electric potential of theelectric discharging power source line 1109 is made higher than theelectric potential of the bias signal line 1106. Thus, from the aboveexplanation, it is necessary that the electric potential of the electricdischarging power source line 1109 be set higher than the electricpotential of the biasing side power source line 1104 but lower than theelectric potential of the bias signal line 1106. Normally, the electricpotential of the electric discharging power source line 1109 may be setequivalent to that of the biasing side power source line 1104.Therefore, the electric discharging power source line 1109 and thebiasing side power source line 1104 may be connected.

[0139] When employing the circuit of FIGS. 11A and 11B in practice, theload capacitance is often connected to the output terminal 1107 tothereby accumulate the signals therein. The diagram of a circuitconfiguration of a case in which the load capacitance is connected tothe circuit illustrated in FIGS. 11A and 11B is shown in FIGS. 1A and1B. One terminal of a load capacitance 110 is connected to an outputterminal 107 whereas the other terminal thereof is connected to a loadcapacitance power source line 111. The electric potential value of theload capacitance power source line 111 may be an arbitrary value.Normally the electric potential value thereof is often set equivalent tothe electric potential of a biasing side power source line 104.Therefore, the load capacitance power source line 111 and the biasingside power source line 104 may be connected. The load capacitance powersource line 111 may also be connected with an amplifying side powersource line 103. Thus, from the above explanation, 2 lines or more fromamong the load capacitance power source line 111, the biasing side powersource line 104, and the electric discharging power source line 109 maybe connected to each other. A circuit configuration and a timing chartof a situation where 3 lines are connected to each other is shown inFIGS. 12A and 12B.

[0140] Explanation has been given so far for the case of using an Nchannel transistor to construct the source follower circuit. However, itis also possible to use a P channel transistor to construct the sourcefollower circuit. Thus, a drawing of circuit configuration using the Pchannel transistor to construct the source follower circuit will beshown next. The case of using the P channel transistor in the circuit ofFIGS. 11A and 11B will be shown in FIGS. 13A and 13B, and a case ofusing the P channel transistor in the circuit of FIGS. 1A and 1B will beshown in FIGS. 14A and 14B. Shown in FIGS. 15A and 15B is a case ofusing the P channel transistor in the circuit of FIGS. 12A and 12B. Whenthe N channel transistor is used to construct the source followercircuit, the electric potential of the amplifying side power source line1103 is higher than the biasing side power source line 1103. However,when the P channel transistor is used to construct the source followercircuit, the electric potential of an amplifying side power source line1303 is lower than the electric potential of a biasing side power sourceline 1304.

[0141] In some cases, a plurality of source follower circuits may bearranged and output terminals may be connected to each other andarranged therein. At that point, there is a necessity to output a signalonly from one source follower circuit. Therefore, a switch may beprovided to stop the flow of an electric current. The diagrams of acircuit configuration and a timing chart of a case where a transferringtransistor 1612 is provided between an output terminal 1607 and a loadcapacitance 1610 in the circuit of FIGS. 1A and 1B is illustrated inFIGS. 16A and 16B. In the circuit of FIGS. 16A and 16B, a switchingtransistor 1713 is provided between an output terminal 1707 and anamplifying transistor 1701, and the circuit configuration and timingchart of this case is illustrated in FIGS. 17A and 17B. In FIGS. 16A and16B or in FIGS. 17A and 17B, at least one element from the amplifyingtransistor, the biasing transistor, and the selecting switch may be usedto construct a unit pixel.

[0142] Note that the switch for stopping the flow of an electric currentmay be formed of either the N channel transistor or the P channeltransistor. In addition, a plurality of switches may be provided and theconnecting method thereof may be in series or in parallel.

[0143] Embodiment Mode 2

[0144] Next, an embodiment mode of a case in which a method ofperforming the pre-discharge is different from that of Embodiment Mode 1is shown in FIGS. 18A and 18B. FIG. 18A is a diagram showing a circuitconfiguration, and FIG. 18B is a diagram showing a signal timing chart.In FIGS. 18A and 18B, pre-discharge is performed by making the biaselectric potential Vb large. Shown in FIGS. 18A and 18B is an example ofa case using an N channel transistor to construct the source followercircuit.

[0145] An electric potential of a gate terminal of an amplifyingtransistor 1801 becomes the input electric potential Vin. This inputelectric potential Vin corresponds to the electric potential of the Nchannel side terminal of the photo diode. A drain terminal of theamplifying transistor 1801 is connected to an amplifying side powersource line 1803, and a source terminal thereof is connected to a drainterminal of a biasing transistor 1802. The source terminal of theamplifying transistor 1801 serves as an output terminal 1807 and anelectric potential thereof becomes the output electric potential Vout.The bias electric potential Vb is applied to a gate terminal of thebiasing transistor 1802. A source terminal of the biasing transistor1802 is connected to a biasing side power source line 1804.

[0146] The bias electric potential Vb is increased during thepre-discharge period. As a result, the electric potential of the outputterminal 1807 becomes the electric potential of a biasing side powersource line 1804 to thereby carry out pre-discharge. During thepre-discharge period, a large electric current can be caused to flow tothe biasing transistor 1802 because the gate electric potential of thebiasing transistor 1802, that is, the bias electric potential Vb islarge. Consequently, the output electric potential Vout can be rapidlylowered, whereby the pre-discharge period is shortened.

[0147] An actual signal is outputted after the pre-discharge. In thatcase, since the source follower circuit is in the Vout<Vin−Vb state, alarge electric current flows to the amplifying transistor 1801 becausethe electric potential between the gate and the source thereof is large.Consequently, the signal writing-in can be done in a short time.

[0148] Taking the input/output relationship of Vout=Vin−Vb intoconsideration, it is appropriate to make the bias electric potential Vbas low as possible when outputting the output electric potential Vout inorder to increase the output electric potential Vout. However, thebiasing transistor 1802 must be in conductive. In other words, thebiasing transistor 1802 must be operable in the saturated region and setat a value in which a fixed electric current can flow therein.Therefore, other than during the pre-discharge period, an optimum valueof an absolute value of a bias signal electric potential (voltagebetween the gate and the source of the biasing transistor) is anelectric potential that is slightly higher than an absolute value of athreshold voltage of the biasing transistor 1802.

[0149] Further, when the bias electric potential Vb is low, theoperating region in which the input/output relationship is linear can bewidened because the biasing transistor 1802 can readily operate in thesaturated region.

[0150] Thus, from the above consequences, it is possible to prevent thesignal writing-in time from becoming long, and enlarging the amplitudeof the output electric potential while widening the operating region inwhich the input/output relationship is linear can be realized at thesame time.

[0151] Regarding the electric potential value of the bias electricpotential Vb during pre-discharge, it is preferable to make the electricpotential value thereof as high as possible in order to performdischarge. Therefore, increasing the bias electric potential Vb until itis as high as the highest electric potential in the circuit, forexample, the amplifying side power source line 1803, is appropriate.

[0152] In the prior art, a fixed electric potential was applied to thebias signal line 1806. In Embodiment Mode 2, the bias electric potentialVb changes during pre-discharge. Therefore, a signal generating devicefor changing the bias electric potential Vb is connected to the biassignal line 1806.

[0153] The explanation so far has been about the case of using an Nchannel transistor to construct the source follower circuit. However, itis also possible to use a P channel transistor to construct the sourcefollower circuit. Thus, a drawing where the P channel transistor is usedto construct the source follower circuit is shown in FIGS. 19A and 19B.Similar to Embodiment Mode 1, the relationship concerning the size ofthe electric potential of the amplifying side power source line and theelectric potential of the biasing side power source line is differentbetween the case of using the N channel transistor to construct thesource follower circuit and the case of using the P channel transistorto construct the source follower circuit.

[0154] Note that similar to Embodiment Mode 1, the provision of a loadcapacitance and a selecting switch is also possible in Embodiment Mode2.

[0155] Embodiment 1

[0156] An embodiment of a case in which pre-discharge is performed byemploying an electric discharging transistor in an area sensor that haspixels arranged two-dimensional therein and incorporated with drivercircuits in the periphery thereof will be explained next. The entirecircuit configuration is illustrated in FIG. 20. First, there isprovided a pixel arrangement portion 2005 having pixels arrangedtwo-dimensional therein. Driver circuits for driving a gate signal lineand a reset signal line of each of the pixels is provided on the leftand right sides of the pixel arrangement portion 2005. In FIG. 20, agate signal line driver circuit 2006 is provided on the left side and areset signal line driver circuit 2007 is provided on the right side.Driver circuits such as a signal processing circuit are arranged abovethe pixel arrangement portion 2005. A biasing circuit 2003 is arrangedabove the pixel arrangement portion 2005 in FIG. 20. The biasing circuit2003 and the amplifying transistors of the respective pixels form thesource follower circuit. A sample hold and signal processing circuit2002 are arranged above the biasing circuit 2003. Circuits formaintaining signals for a time, for performing analog/digitalconversion, or for reducing noise are arranged here. A signal outputline driver circuit 2001 is arranged above the sample hold and signalprocessing circuit 2002. The signal output line driver circuit 2001outputs signals for outputting, in sequence, the signals that have beentemporarily preserved. Then, before the signals are outputted to theoutside, a final output amplifying circuit 2004 is arranged thereto.Before the signals, which are sequentially outputted hereto by thesample hold and the signal processing circuit 2002 and the signal outputline driver circuit 2001, are outputted to the outside, the signals areamplified by the final output amplifying circuit 2004. Therefore,although unnecessary when the signals are not amplified, in practice itis often provided.

[0157] Next, the circuit configuration of the respective portions isillustrated. First, taking an ith line jth row pixel portion circuit2008 as an example from the interior of the pixel arrangement portion2005 having pixels arranged in two-dimensional, the circuitconfiguration thereof is shown in FIG. 21. In FIG. 21, the ith line jthrow pixel portion circuit 2008 is composed of a P channel resettingtransistor 2107, a P channel switching transistor 2101, an N channelamplifying transistor 2106, and a photoelectric conversion element(here, it is the most typical photo diode 2104). A P channel sideterminal of the photo diode 2104 is connected to a power source standardline 2112, and an N channel side terminal thereof is connected to a gateterminal of the amplifying transistor 2106. An ith line resetting signalline 2105 is connected to a gate terminal of the resetting transistor2107. A source terminal and a drain terminal of the resetting transistor2107 are connected to a jth row power source line 2109 and to the gateterminal of the amplifying transistor 2106. A gate terminal of theswitching transistor 2101 is connected to an ith line gate signal line2102, and a source terminal and a drain terminal thereof are connectedto the jth row power source line 2109 and to the gate terminal of theamplifying transistor 2106. A source terminal and a drain terminal ofthe amplifying transistor 2106 are connected to a jth row signal outputline 2103 and to the switching transistor 2101. As in the prior art, theith line gate signal line 2102 and the ith line resetting signal line2105 have their wirings extended in the horizontal direction.

[0158] If the wirings of this circuit configuration is madecorresponding to the wirings of the source follower circuit, the jth rowpower source line 2109 corresponds to the amplifying side power sourceline 1103, the power source standard line 2112 corresponds to thebiasing side power source line 1104, and the output terminal 1107corresponds to the jth row signal output line 2103.

[0159] In FIG. 21, the resetting transistor 2107 is formed of the Pchannel type. However, the resetting transistor 2107 maybe formed of theN channel type. Note that, the voltage between the gate and the sourceof the resetting transistor 2107 cannot be large during the resettingoperation in the case the N channel type is used to form the resettingtransistor 2107. Accordingly, the resetting transistor will operate inthe saturated region, whereby the photo diode 2104 cannot be chargedsufficiently. As a result, though the resetting transistor 2107 willoperate even if it is formed of the N channel type, it is desirable touse a P channel type.

[0160] As for the switching transistor 2101, it is arranged between theith line power source line 2109 and the amplifying transistor 2106, andis desirably formed of the P channel type as well. However, similar tothe prior art, since the switching transistor can operate even if it isformed of N channel type, the N channel type may be used. The switchingtransistor 2101 may also be provided between the jth row signal outputline 2103 and the amplifying transistor 2106. However, because there isdifficulty in outputting a signal correctly, the switching transistor2101 is arranged between the ith line power source line 2109 and theamplifying transistor 2106, and is desirably formed of the P channeltype.

[0161] As for the amplifying transistor 2106 in FIG. 21, the N channeltype is used. Nonetheless, the P channel type may be used. However, inthe case of using the P channel type, it is necessary to change theconnection method of the circuit in order to combine the amplifyingtransistor with the biasing transistor to thereby operate as the sourcefollower circuit. That is, in the circuit configuration of FIG. 21, theamplifying transistor 2106 will not operate by simply changing thepolarity thereof.

[0162] Then, an example of a circuit configuration when a P channel typeof amplifying transistor is used is shown in FIG. 22. The differencesbetween this circuit configuration and that of FIG. 21 is that thepolarity of an amplifying transistor 2206 is the P channel type, thedirection in which the photo diode faces is inverted, and the powersource line and the power source standard line are changed. In the caseof using the P channel type in the amplifying transistor, it isnecessary to use the P channel type in the biasing transistor also. Thereason for this resides in that there is a necessity to operate thebiasing transistor as a fixed electric current source. Therefore, adescription of a biasing transistor 2211 is also made in FIG. 22 forreference. The ith line jth row pixel portion circuit 2008 illustratedin FIG. 22 is composed of an N channel type resetting transistor 2207,an N channel type switching transistor 2201, a P channel type amplifyingtransistor 2206, and a photoelectric conversion element (here, it is themost typical photo diode 2204). An N channel side terminal of the photodiode 2204 is connected to a power source line 2209, and a P channelside terminal thereof is connected to a gate terminal of an amplifyingtransistor 2206. An ith line resetting signal line 2205 is connected toa gate terminal of the resetting transistor 2207. A source terminal anda drain terminal of the resetting transistor 2207 are connected to a jthrow power source standard line 2212 and to the gate terminal of theamplifying transistor 2206. A gate terminal of the switching transistor2201 is connected to an ith line gate signal line 2202, and a sourceterminal and a drain terminal thereof are connected to the jth row powersource standard line 2212 and the amplifying transistor 2206. A sourceterminal and a drain terminal of the amplifying transistor 2206 areconnected to a jth row signal output line 2203 and to the switchingtransistor 2201. A biasing signal line 2210 is connected to a gateterminal of the biasing transistor 2211, and a source terminal and agate terminal thereof are connected to the jth row signal output line2203 and to the power source line 2209.

[0163] When the wirings of this circuit configuration is madecorresponding to the wirings of the source follower circuit, then thejth row power source standard line 2212 corresponds to the amplifyingside power source line 1803, the power source line 2109 corresponds tothe biasing side power source line 1804, and the output terminal 1807corresponds to the jth row signal output line 2203.

[0164] In FIG. 22, the N channel type is used for the resettingtransistor 2207. However, the resetting transistor 2207 may also beformed of the P channel type. However, the voltage between the gate andthe source of the resetting transistor 2207 cannot be large during theresetting operation in the case where the P channel type is used to formthe resetting transistor 2207. Accordingly, the resetting transistorwill operate in the saturated region, whereby the photo diode 2204cannot be charged sufficiently. As a result, though the resettingtransistor 2207 will operate even if the P channel type is used, it isdesirable to use the N channel type.

[0165] As for the switching transistor 2201 in FIG. 22, it is arrangedbetween the jth row power source standard line 2212 and the amplifyingtransistor 2206, and desirably is formed of N channel type as well.However, since the switching transistor can operate even if it is formedof the P channel type, the P channel type may also be used. Theswitching transistor 2201 may also be provided between the jth rowsignal output line 2203 and the amplifying transistor 2206. However,because there is difficulty in outputting a signal correctly, theswitching transistor 2201 is arranged between the jth row power sourcestandard line 2212 and the amplifying transistor 2206, and is desirablyformed by using the N channel type.

[0166] Thus, as is apparent from the comparison between the circuitconfigurations of FIG. 21 and 22, when the polarity of the amplifyingtransistors is different, the optimal transistor structure also differs.

[0167] Next, the circuit configuration of a jth row peripheral portioncircuit 2009 taken as an exemplary row of circuits from inside thebiasing circuit 2003 and the sample hold and signal processing circuit2002 is shown in FIG. 23. A biasing transistor 2311 is arranged in thebiasing circuit 2003. The polarity thereof is the same as the polarityof the amplifying transistor of the respective pixels. Therefore, if theamplifying transistor of the pixel is the N channel type, the biasingtransistor is also the N channel type. In FIG. 23, the biasingtransistor 2311 is the N channel type. A gate terminal of the biasingtransistor 2311 is connected to a biasing signal line 2310, and a sourceterminal and a drain terminal thereof are connected to a jth row signaloutput line 2303 and a power source standard line 2312 (when the biasingtransistor is the P channel type, the power source line is used in placeof the power source standard line). The biasing transistor 2311 and theamplifying transistors of the respective pixels, operates as the sourcefollower circuit. A gate terminal of a transferring transistor 2313 isconnected to a transfer signal line 2314, and a source terminal and adrain terminal thereof are connected to a jth row signal output line2303 and a load capacitance 2315. The transferring transistor isoperated when transferring the electric potential of the signal outputline 2303 to the load capacitance 2315. Therefore, a P channel typetransferring transistor may be added and connected in a row to an Nchannel type transferring transistor 2314. The load capacitance 2315 isconnected to the transferring transistor 2313 and the power sourcestandard line 2312. The role of the load capacitance 2315 is totemporarily accumulate therein the signals outputted from the signaloutput line 2303. A gate terminal of an electric discharging transistor2316 is connected to a pre-discharge signal line 2317, and a sourceterminal and a drain terminal thereof are connected to the loadcapacitance 2315 and the power source standard line 2312. Prior toinputting the electric potential of the signal output line 2303 to theload capacitance 2315, the electric discharging transistor 2316 operatesto discharge the electric charges that have temporarily accumulated inthe load capacitance 2315.

[0168] Note that the analog/digital signal conversion circuit, the noisereduction circuit, etc. may also be arranged therein.

[0169] A final selecting transistor 2319 is connected between the loadcapacitance 2315 and a final output line 2320. A source terminal and adrain terminal of the final selecting transistor 2319 are connected tothe load capacitance 2315 and the final output line 2320, and a gateterminal thereof is connected to a jth row final selecting line 2318.The final selecting line will be scanned from the first row in sequence.Then the jth row final selecting line 2318 is selected, and when thefinal selecting transistor 2319 is turned into conductive, the electricpotential of the load capacitance 2315 and that of the final output line2320 become equivalent. As a result, the signals that have accumulatedin the load capacitance 2315 can be outputted to the final output line2320. However, if electric charges are accumulated in the final outputline 2320 before outputting the signals to the final output line 2320,the electric potential when outputting the signals to the final outputline 2320 will be adversely influenced by those electric charges.Therefore, the electric potential of the final output line 2320 must beinitialized to a certain electric potential value before the signals areoutputted to the final output line 2320. In FIG. 23, a final resettingtransistor 2322 is arranged between the final output line 2320 and thepower source standard line 2312. A gate terminal of the final resettingtransistor 2322 is connected to a jth row final resetting line 2321.Prior to selecting the jth row final selecting line 2318, the jth rowfinal resetting line 2321 is selected to thereby initialize the electricpotential of the final output line 2320 and that of the power sourcestandard line 2312. Thereafter, the jth row final selecting line 2318 isselected, whereby the signals that have accumulated in the loadcapacitance 2315 are outputted to the final output line 2320.

[0170] The signals that will be outputted to the final output line 2320may be withdrawn to the outside. However, because the signals are faint,the signals are frequently amplified before being withdrawn to theoutside. As a circuit for carrying out the amplification of the signals,the circuit configuration of the final portion circuit 2010 is shown inFIG. 24. There are various kinds of circuits for amplifying the signals,such as an arithmetic amplifier. Any kind of circuit that can amplifythe signals may be used. As the most simple circuit configuration, thesource follower circuit is shown here. In FIG. 24, the N channel type isillustrated. Signals that are inputted to the final output amplifyingcircuit 2004 will be inputted to a final output line 2402. Signals areoutputted from the first row in sequence from the final output line2402. The signals are amplified by the final output amplifying circuit2004 and then outputted to the outside. The final output line 2402 isconnected to a gate terminal of a final output amplifier-amplifyingtransistor 2404. A drain terminal of the final outputamplifier-amplifying transistor 2404 is connected a power source line2404, and a source terminal thereof serves as an output terminal. A gateterminal of a final output amplifier-biasing transistor 2403 isconnected to a final output amplifying bias signal line 2405, and asource terminal and a drain terminal thereof are connected to a powersource standard line 2407 and a source terminal of the final outputamplifier-amplifying transistor 2404.

[0171] Shown in FIG. 25 is a circuit configuration of the sourcefollower circuit when the P channel type is used. The difference fromthe circuit configuration of FIG. 24 is that the power source line andthe power source standard line are reversed. A final output line 2502 isconnected to a gate terminal of a final output amplifier-amplifyingtransistor 2504. A drain terminal of the final outputamplifier-amplifying transistor 2504 is connected to a power sourcestandard line 2507, and a source terminal thereof serves as an outputterminal. A gate terminal of a final output amplifier-biasing transistor2503 is connected to a final output amplifying bias signal line 2505. Asource terminal and a drain terminal of the final outputamplifier-biasing transistor 2503 are connected to a power source line2506 and a source terminal of the final output amplifier-amplifyingtransistor 2504. A value of the electric potential of the final outputamplifying bias signal line 2505 is different from that of the finaloutput amplifying bias signal line 2405 in the case where the N channeltype is used.

[0172] In FIGS. 24 and 25, the source follower circuit is constructed ofonly one level. However, it may also be constructed of plural levels.For example, in the case of constructing the source follower circuit in2 levels, the output terminal of the first level may be connected to theinput terminal of the second level. In addition, in each of the levels,either the N channel type or the P channel type may be used.

[0173] The gate signal line and reset signal line driver circuit 2006,the power source line driver circuit 2207, and a signal output linedriver circuit AZO1 are circuits which simply output pulse signals.Therefore, implementation thereof can be made by employing a knowntechnique.

[0174] A timing chart of a signal will be explained next. The timingchart of the circuit shown in FIG. 20 is illustrated in FIG. 26. Thereset signal line is scanned sequentially from the first line. Forexample, first an (i−1)th line is selected, followed by an ith line, andthen an (i+1)th line is selected. A period until the same line isselected again corresponds to a frame period. Similarly, the gate signalline is sequentially scanned from the first line. However, the timing tostart scanning the gate signal line is later than the timing to startscanning the reset signal line. For instance, directing the attention toa pixel of the ith line, the ith line reset signal line is selected, andthereafter the ith line gate signal line is selected. When the ith linegate signal line is selected, a signal is outputted from the pixel ofthe ith line. A period from the time the pixel is reset until the signalis outputted becomes an accumulation time. During the accumulation time,electric charges generated by light are being accumulated in the photodiode. The timing to reset and the timing to output a signal aredifferent in each line. Therefore, although the accumulation time of thepixels in all the lines are equivalent, the time that signals areaccumulated therein is different.

[0175] Next, the timing chart of a signal of FIG. 23 is shown in FIG.27. Because the operation is repetitious, the time that the ith linegate signal line is selected will be taken as an example and observed.First, after the ith line gate signal line 2102 is selected, thepre-discharge signal line 2317 is selected to thereby make the electricdischarging transistor 2316 in conductive. Subsequently, the transfersignal line 2314 is selected, whereby the signal of each of the rowsfrom the ith line pixel is outputted to the load capacitance 2315 ofevery row.

[0176] After accumulating the signals of all the pixels of the ith linein the load capacitance 2315 of every row, the signals of every row aresequentially outputted to the final output line 2320. During the periodfrom the time the transfer signal line 2314 has become non-selective tothe time the gate signal line is selected, all the rows are scanned bythe signal output line driver circuit 2001. First, the final reset lineof the first row is selected to thereby make the final resettingtransistor 2322 into conductive, whereby the electric potential of thefinal output line 2320 is initialized to that of the power sourcestandard line 2312. Thereafter, the final selecting line 2318 of thefirst row is selected and the final selecting transistor 2319 is turnedinto conductive to thereby output the signal in the load capacitance2315 of the first row to the final output line 2320. Next, the finalreset line of the second row is selected to thereby make the finalresetting transistor 2322 into conductive, whereby the electricpotential of the final output line 2320 is initialized to that of thepower source standard line 2312. Thereafter, the final selecting line2318 of the second row is selected and the final selecting transistor2319 is turned into conductive to thereby output the signal in the loadcapacitance 2315 of the second row to the final output line 2320. Theoperation is repeated thereafter. Similarly, in the case of the jthline, the final reset line of the jth row is selected to thereby makethe final resetting transistor 2322 into conductive, whereby theelectric potential of the final output line 2320 is initialized to thatof the power source standard line 2312. Thereafter, the final selectingline 2318 of the jth row is selected and the final selecting transistor2319 is turned into conductive to thereby output the signal in the loadcapacitance 2315 of the jth row to the final output line 2320. Next, thefinal reset line of the (j+1)th row is selected and the final resettingtransistor 2322 is turned into conductive, whereby the electricpotential of the final output line 2320 is initialized to that of thepower source standard line 2312. Thereafter, the final selecting line2318 of the (j+1)th row is selected and the final selecting transistor2319 is turned into conductive to thereby output the signal in the loadcapacitance 2315 of the (j+1)th row to the final output line 2320. Thesame operation is repeated thereafter to sequentially output all thesignals to the final output line. During this operation, the bias signalline 2310 is fixed. The signals outputted to the final output line 2320are amplified by the final output amplifying circuit 2004 and thenoutputted to the outside.

[0177] Next, the (i+1)th line gate signal line is selected. The sameoperation as performed when the ith line gate signal line was selectedwill be performed. Then, the gate signal line of the next line will beselected further and the same operation will be repeated.

[0178] The electric potential of the bias signal line 2310 will beexplained here. In FIG. 23, a plural number of the biasing transistor2311 is provided. Therefore, even if there is a fluctuation in thethreshold voltages of the plural number of the biasing transistor 2311,all the biasing transistors 2311 must be in conductive. As a result, itis necessary to make the absolute value of the voltage between the gateand the source of the biasing transistor equivalent to the minimum valueof the absolute value of the voltage between the gate and the sourcethereof in order to turn all the biasing transistors into conductive.

[0179] Note that as for the sensor portion in which photoelectricconversion is performed, other than the usual PN type of photo diode, aPIN type diode, an avalanche diode, an NPN incorporated diode, aSchottky diode, an X-ray photo conductor, and a sensor for infrared raysor the like may be used. In addition, X-rays may be converted into lightby using a fluorescent material or a scintillator and thereafter readthe light that has been converted.

[0180] As explained so far, the photoelectric conversion element isoften connected to the input terminal of the source follower circuit.However, a switch may be sandwiched therebetween like a photo gate type,or the signal, after it has been processed so that it is a logarithmicvalue of light density, may be inputted to the input terminal, like alogarithm conversion type.

[0181] Although the area sensor having pixels arranged intwo-dimensional therein was explained in Embodiment 1, a line sensorhaving pixels arrange in one-dimensional can also be realized.

[0182] Embodiment 2

[0183] In Embodiment 2, a case in which pre-discharge is performed bycontrolling a bias signal line in an area sensor that has pixelsarranged in two-dimensional therein and incorporated with drivercircuits in the periphery thereof will be explained next. The Embodiment2 is different from Embodiment 1 only with respect to a portion of thecircuit configuration (FIG. 23) and a portion of the signal timing chart(FIG. 27). Therefore, a circuit configuration thereof corresponding tothat of FIG. 23 is shown in FIG. 29, and a timing chart of a signalthereof corresponding to that of FIG. 27 is shown in FIG. 28.

[0184] The circuit configuration of FIG. 29 is one in which the electricdischarging transistor 2316 and the pre-discharge signal line 2317 areremoved from the circuit configuration of FIG. 23.

[0185] Next, the timing chart of a signal in FIG. 29 is shown in FIG.28. Because the operation is repetitious, the case in which the ith linegate signal line is selected will be taken as an example and observed.First, after the ith line gate signal line 2102 is selected, theelectric potential of a bias signal line 2910 and that of a transferringtransistor 2913 are raised to thereby perform pre-discharge. Then theelectric potential of the bias signal line 2910 is returned to itsoriginal value, whereby the signal of each of the rows from the ith linepixels is outputted to a load capacitance 2915 of every row. The signalof each of the rows is sequentially outputted to a final output line2920 after the signals of all the ith line pixels have accumulated inthe load capacitance 2915 of every row.

[0186] Note that in Embodiment 2, the bias electric potential Vb changesduring pre-discharge. Therefore, a signal generating device for changingthe bias electric potential Vb may be connected to the bias signal line2910.

[0187] Embodiment 3

[0188] A method of manufacturing a sensor portion using TFT on the glassof this invention is explained using FIGS. 30 to 33.

[0189] First, as shown in FIG. 30A, a base film 201 is formed to athickness of 300 nm on a glass substrate 200. A silicon oxinitride filmis laminated as the base film 201 in Embodiment 3. At this point, it isappropriate to set the nitrogen concentration to between 10 and 25 wt %in the film contacting the glass substrate 200. In addition, it iseffective that the base film 201 has a thermal radiation effect, and aDLC (diamond-like carbon) film may also be provided.

[0190] Next, an amorphous silicon film (not shown in the figure) isformed with a thickness of 50 nm on the base film 201 by a knowndeposition method. Note that it is not necessary to limit to theamorphous silicon film, and a semiconductor film containing an amorphousstructure (including a microcrystalline semiconductor film)may be used.In addition, a compound semiconductor film containing an amorphousstructure, such as an amorphous silicon germanium film, may also beused. Further, the film thickness may be made from 20 to 100 nm.

[0191] The amorphous silicon film is then crystallized by a knowntechnique, forming a crystalline silicon film (also referred to as apolycrystalline silicon film or a polysilicon film) 202. There arethermal crystallization using an electric furnace, laser annealingcrystallization using a laser light, and lamp annealing crystallizationusing an infrared light as known crystallization methods.Crystallization is performed in Embodiment 3 using an excimer laserlight, which uses XeCl gas.

[0192] Note that pulse emission excimer laser light formed into a linearshape is used in Embodiment 3, but a rectangular shape may also be used.Continuous emission type argon laser light and continuous emission typeexcimer laser light can also be used.

[0193] In this embodiment, although the crystalline silicon film is usedas the active layer of the TFT, it is also possible to use an amorphoussilicon film as the active layer.

[0194] Note that it is effective to form the active layer of thetransistor for reset, in which there is a necessity to reduce the offcurrent, by the amorphous silicon film, and to form the active layer ofthe transistor for amplification by the crystalline silicon film.Electric current flows with difficulty in the amorphous silicon filmbecause the carrier mobility is low, and the off current does not easilyflow. In other words, the most can be made of the advantages of both theamorphous silicon film, through which current does not flow easily, andthe crystalline silicon film, through which current easily flows.

[0195] Next, as shown in FIG. 30B, a protective film 203 is formed onthe crystalline silicon film 202 with a silicon oxide film having athickness of 130 nm. This thickness may be chosen within the range of100 to 200 nm (preferably between 130 and 170 nm). Furthermore, anotherfilms such as insulating films containing silicon may also be used. Theprotective film 203 is formed so that the crystalline silicon film isnot directly exposed to plasma during addition of an impurity, and sothat it is possible to have delicate concentration control of theimpurity.

[0196] Resist masks 204 a, 204 b, and 204 c are then formed on theprotective film 203, and an impurity element, which imparts n-typeconductivity (hereafter referred to as an n-type impurity element), isadded through the protective film 203. Note that elements residing inperiodic table group 15 are generally used as the n-type impurityelement, and typically phosphorous or arsenic can be used. Note that aplasma doping method is used, in which phosphine (PH₃) is plasma-excitedwithout separation of mass, and phosphorous is added at a concentrationof 1×10¹⁸ atoms/cm³in Embodiment 3. An ion implantation method, in whichseparation of mass is performed, may also be used, of course.

[0197] The dose amount is regulated such that the n-type impurityelement is contained in n-type impurity regions (b) 205 a, 205 b thusformed by this process, at a concentration of 2×10¹⁶ to 5×10¹⁹ atoms/cm³(typically between 5×10¹⁷ and 5×10¹⁸ atoms/cm³).

[0198] Next, as shown in FIG. 30C, the protective film 203 and theresist masks 204 a, 204 b, and 204 c are removed, and an activation ofthe added n-type impurity elements is performed. A known technique ofactivation may be used as the means of activation, but activation isdone in Embodiment 3 by irradiation of excimer laser light (laserannealing). Of course, a pulse emission excimer laser and a continuousemission excimer laser may both, be used, and it is not necessary toplace any limits on the use of excimer laser light. The goal is theactivation of the added impurity element, and it is preferable thatirradiation is performed at an energy level at which the crystallinesilicon film does not melt. Note that the laser irradiation may also beperformed with the protective film 203 in place.

[0199] The activation of impurity elements by heat treatment (furnaceannealing) may also be performed along with activation of the impurityelement by laser light. When activation is performed by heat treatment,considering the heat resistance of the substrate, it is good to performheat treatment at about 450 to 550° C.

[0200] A boundary portion (connecting portion) with end portions of then-type impurity regions (b) 205 a, 205 b, namely regions, in which then-type impurity element is not added, on the periphery of the n-typeimpurity regions (b) 205 a, 205 b, is delineated by this process. Thismeans that, at the point when the TFTs are later completed, extremelygood connecting portion can be formed between LDD regions and channelforming regions.

[0201] Unnecessary portions of the crystalline silicon film are removednext, as shown in FIG. 30D, and island-shape semiconductor films(hereinafter referred to as active layers) 206 to 210 are formed.

[0202] Then, as shown in FIG. 31A, a gate insulating film 211 is formed,covering the active layers 206 to 210. An insulating film containingsilicon and with a thickness of 10 to 200 nm, preferably between 50 and150 nm, may be used as the gate insulating film 211. A single layerstructure or a lamination structure may be used. A 110 nm thick siliconoxinitride film is used in Embodiment 3.

[0203] Thereafter, a conductive film having a thickness of 200 to 400 nmis formed and patterned to form gate electrodes 212 to 216. InEmbodiment 3, the gate electrodes and wirings (hereinafter referred toas gate wirings) electrically connected to the gate electrodes forproviding conductive paths are formed of the same materials. Of course,the gate electrode and the gate wiring may be formed of differentmaterials from each other. More specifically, the gate wirings are madeof a material having a lower resistivity than the gate electrodes. Thisis because a material enabling fine processing is used for the gateelectrodes, while the gate wirings are formed of a material that canprovide a smaller wiring resistance but is not suitable for fineprocessing. The wiring resistance of the gate wiring can be madeextremely small by using this type of structure, and therefore a sensorportion having a large surface area can be formed. Namely, the abovedescribed pixel structure is extremely effective when an area sensorwith a sensor portion having a screen size of a 10 inch diagonal orlarger (in addition, a 30 inch or larger diagonal) is realized.

[0204] Although the gate electrode can be made of a single-layeredconductive film, it is preferable to form a lamination film with twolayers or three layers, if necessary. Any known conductive films can beused for the gate electrodes 212 to 216.

[0205] Typically, it is possible to use a film made of an elementselected from the group consisting of aluminum (Al), tantalum (Ta),titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon(Si), a film of nitride of the above element (typically a tantalumnitride film, tungsten nitride film, or titanium nitride film), an alloyfilm of combination of the above elements (typically Mo-W alloy or Mo-Taalloy), or a silicide film of the above element (typically a tungstensilicide film or titanium silicide film). Of course, the films may beused as a single layer or a laminate layer.

[0206] In Embodiment 3, a laminate film of a tungsten nitride (WN) filmhaving a thickness of 30 nm and a tungsten (W) film having a thicknessof 370 nm is used. This may be formed by sputtering. When an inert gassuch as Xe or Ne is added as a sputtering gas, film peeling due tostress can be prevented.

[0207] The gate electrodes 213 and 216 are respectively formed at thistime so as to overlap a portion of the n-type impurity regions (b) 205 aand 205 b through the gate insulating film 211. This overlapping portionlater becomes an LDD region overlapping the gate electrode.

[0208] Next, an n-type impurity element (phosphorous is used inEmbodiment 3) is added in a self-aligning manner with the gateelectrodes 212 to 216 as masks, as shown in FIG. 31B. The addition isregulated such that phosphorous is added to n-type impurity regions (c)217 to 224 thus formed at a concentration of {fraction (1/10)} to ½ thatof the n-type impurity regions (b) 205 a and 205 b (typically between ¼and ⅓). Specifically, a concentration of 1×10¹⁶ to 5×10¹⁸ atoms/cm³(typically 3×10¹⁷ to 3×10¹⁸ atoms/cm³) is preferable.

[0209] Resist masks 225 a to 225 c are formed next, with a shapecovering the gate electrodes 212, 214 and 215, as shown in FIG. 31C, andan n-type impurity element (phosphorous is used in Embodiment 3) isadded, forming impurity regions (a) 226 to 233 containing phosphorous athigh concentration. Ion doping using phosphine (PH₃) is also performedhere, and the phosphorous concentration of these regions is regulated soas to be set to from 1×10²⁰ to 1×10²¹ atoms/cm³ (typically between2×10²⁰ and 5×10²¹ atoms/cm³).

[0210] A source region or a drain region of the n-channel TFT is formedby this process, and in the n-channel TFT, a portion of the n-typeimpurity regions (c) 217, 218, 222, and 223 formed by the process ofFIG. 31B is remained. These remaining regions correspond to LDD regions.

[0211] Next, as shown in FIG. 31D, the resist masks 225 a to 225 c areremoved, and new resist masks 234 a and 234 b are formed. A p-typeimpurity element (boron is used in Embodiment 3) is then added, formingp-type impurity regions 235 and 236 containing boron at highconcentration. Boron is added here at a concentration of 3×10²⁰ to3×10²¹ atoms/cm³ (typically between 5×10²⁰ and 1×10²¹ atoms/cm³) by iondoping using diborane (B₂H₆).

[0212] Note that phosphorous has already been added to the impurityregions 235 and 236 at a concentration of 1×10²⁰ to 1×10²¹ atoms/cm³,but boron is added here at a concentration of at least 3 times or morethat of the phosphorous. Therefore, the n-type impurity regions alreadyformed completely invert to p-type, and function as p-type impurityregions.

[0213] Next, after removing the resist masks 234 a and 234 b, the n-typeor p-type impurity elements added to the active layer at respectiveconcentrations are activated. Furnace annealing, laser annealing or lampannealing can be used as a means of activation. In Embodiment 3, heattreatment is performed for 4 hours at 550° C. in a nitrogen atmospherein an electric furnace.

[0214] At this time, it is important to eliminate oxygen from thesurrounding atmosphere as much as possible. This is because an exposedsurface of the gate electrode is oxidized, which results in an increasedresistance if only a small amount of oxygen exists. Accordingly, theoxygen concentration in the surrounding atmosphere for the activationprocess is set at 1 ppm or less, preferably at 0.1 ppm or less.

[0215] A first interlayer insulating film 237 is formed next, as shownin FIG. 32A. A single layer insulating film containing silicon is usedas the first interlayer insulating film 237, or a lamination film may beused. Further, a film thickness of between 400 nm and 1.5 μm may beused. A lamination structure of a silicon oxide film having a thicknessof 800 nm on a silicon oxinitride film having a thickness of 200 nmthick is used in Embodiment 3.

[0216] In addition, heat treatment is performed for 1 to 12 hours at 300to 450° C. in an atmosphere containing between 3 and 100% hydrogen,performing hydrogenation. This process is one of hydrogen termination ofdangling bonds in the semiconductor film by hydrogen, which is thermallyexcited. Plasma hydrogenation (using hydrogen excited by plasma) mayalso be performed as another means of hydrogenation.

[0217] Note that the hydrogenation processing may also be insertedduring the formation of the first interlayer insulating film 237.Namely, hydrogen processing maybe performed as above after forming the200 nm thick silicon oxinitride film, and then the remaining 800 nmthick silicon oxide film may be formed.

[0218] Next, a contact hole is formed in the gate insulating film 211and the first interlayer insulating film 237, and source wirings 238 to242 and drain wirings 243 to 247 are formed. In this embodiment, thiselectrode is made of a laminate film of three-layer structure in which atitanium film having a thickness of 100 nm, an aluminum film containingtitanium and having a thickness of 300 nm, and a titanium film having athickness of 150 nm are continuously formed by sputtering. Of course,other conductive films may be used.

[0219] A first passivation film 248 is formed next with a thickness of50 to 500 nm (typically between 200 and 300 nm). A 300 nm thick siliconoxinitride film is used as the first passivation film 248 in Embodiment3. This may also be substituted by a silicon nitride film. Note that itis effective to perform plasma processing using a gas containinghydrogen such as H₂ or NH₃ before the formation of the siliconoxinitride film. Hydrogen activated by this preprocess is supplied tothe first interlayer insulating film 237, and the film quality of thefirst passivation film 248 is improved by performing heat treatment. Atthe same time, the hydrogen added to the first interlayer insulatingfilm 237 diffuses to the lower side, and the active layers can behydrogenated effectively.

[0220] Next, a second interlayer insulating film 249 made of organicresin is formed as shown in FIG. 32B. As the organic resin, it ispossible to use polyimide, polyamide, acryl, BCB (benzocyclobutene) orthe like. Especially, since the second interlayer insulating film 249 isprimarily used for leveling, acryl excellent in leveling properties ispreferable. In this embodiment, an acrylic film is formed to a thicknesssufficient to level a stepped portion formed by TFTs. It is appropriatethat the thickness is made 1 to 5 μm (more preferably, 2 to 4 μm).

[0221] Next, a contact hole is formed in the second interlayerinsulating film 249 and the first passivation film 248 so as to reachthe drain wiring 245, and a cathode electrode 250 of a photodiode isformed so as to contact the drain wiring 245. In embodiment 3, analuminum film formed by sputtering is used as the cathode electrode 250,but other metals, for example titanium, tantalum, tungsten, and coppercan also be used. Further, a lamination film made from titanium,aluminum, and titanium may also be used.

[0222] Patterning is next performed after depositing an amorphoussilicon film containing hydrogen over the entire surface of thesubstrate, and a photoelectric conversion layer 251 is formed. Then, atransparent conductive film is formed on the entire surface of thesubstrate. A 200 nm thick ITO film is deposited by sputtering as thetransparent conductive film in Embodiment 3. The transparent conductivefilm is patterned, forming an anode electrode 252. (FIG. 32C.)

[0223] A third interlayer insulating film 253 is then formed, as shownin FIG. 33A. A level surface can be obtained by using a resin such aspolyimide, polyamide, polyimide amide, or acrylic as the thirdinterlayer insulating film 253. A polyimide film having a thickness of0.7 μm is formed over the entire surface of the substrate as the thirdinterlayer insulating film 253 in Embodiment 3.

[0224] A contact hole is next formed in the third interlayer insulatingfilm 253 so as to reach the anode electrode 252, and a sensor wiring 254is formed. A 300 nm thick aluminum alloy film (an aluminum filmcomprising titanium of 1 wt %) is formed in Embodiment 3.

[0225] The sensor substrate is formed which has the structure as shownin FIG. 33B.

[0226] Reference numeral 270 shows an amplifier TFT, 271 shows aswitching TFT, 272 shows reset TFT, 273 shows a bias TFT, and 274 showsdischarge TFT.

[0227] In embodiment 3, the amplifier TFT 270 and the bias TFT 273 arean n-channel TFT, and both of source region side and drain region sidehave LDD regions 281 to 284. Note that the LDD regions 281 to 284 do notoverlap with the gate electrodes 212 and 215 through the gate insulatingfilm 211. The above constitution of the amplifier TFT 270 and the biasTFT 273 can reduce the hot carrier injection as much as possible.

[0228] Further in Embodiment 3, the switching TFT 271 and the dischargeTFT 274 is a n-channel TFT, each TFTs has LDD regions 283 and 286 ononly the drain region side. The LDD region 283 and 286 are overlapped tothe gate electrode 213 and 216 interposing the gate insulating film 211.

[0229] The formation of the LDD regions 283 and 286 on only the drainregion side is in consideration of reducing the hot carrier injectionand not causing the operating speed to drop. Further, it is notnecessary to be too concerned with the value of the off current for theswitching TFT 271 and the discharge TFT 274, and more importance may beplaced on the operating speed. It is therefore preferable for the LDDregions 283 and 286 to completely overlap with the gate electrodes 213and 216, and to reduce resistive components as much as possible. Namely,the so-called offset should be eliminated. In particular, when thesource signal line driver circuit or the gate signal line drivingcircuit is driven at 15 V to 20 V, the above constitution of thedischarge TFT 274 of Embodiment 3 is effective to reduce the hot carrierinjection and also not to drop the operation speed.

[0230] Furthermore, in Embodiment 3, a reset TFT 272 is p-channel TFTand has no LDD region. Degradation due to hot carrier injection isalmost of no concern for the p-channel TFTs, and therefore LDD regionsdo not have to be formed in particular. It is also possible, of course,to form an LDD region similar to that of an n-channel TFT to take actionagainst hot carriers. Further, the reset TFT 272 may be an n-channeltype TFT.

[0231] The device is completed as a manufactured product by attaching aconnector (flexible printed circuit, FPC) for connecting terminalspulled around from the elements or circuits formed on the substrate withexternal signal terminals.

[0232] The sensor is formed by using a TFT on the glass or thephotodiode in this embodiment, the transistor on the single crystallinesilicon substrate can also be used.

[0233] Embodiment 4

[0234] The sensor manufactured by implementing the present invention canbe used for various kinds of electronic equipments. The following can begiven as such electronic equipment according to the present invention: ascanner; a digital still camera; an x-ray camera; a portable informationterminal (a mobile computer, a portable telephone, and a portable gamemachine); a notebook type personal computer; a game apparatus; a videotelephone, etc.

[0235]FIG. 34A is a scanner, and contains a reading region 3402, asensor portion 3401, a reading operation start switch 3404 and the like.The present invention can be used as the sensor portion 3401.

[0236]FIG. 34B is a digital still camera, and contains a finder 3405, asensor portion 3404, a shutter button 3406 and the like. The presentinvention can be used as the sensor portion 3404.

[0237]FIG. 35 is an x-ray camera, and contains an x-ray generator 3501,a sensor portion 3503, a computer 3054 for signal processing and thelike. An object 3502 to be examined stands between the x-ray generator3501 and the sensor portion 3503, and the x-ray photograph is taken. Thepresent invention can be used as the sensor portion 3503.

[0238]FIG. 36 is a personal computer, and contains a main body 3601, acasing 3602, a display 3603, a keyboard 3604, a sensor portion 3605 andthe like. The present invention can be used as the display 3603 and thesensor portion 3605.

[0239] Here, FIG. 37 shows a portable telephone, and contains a mainbody 3701, a sound output portion 3702, a sound input portion 3703, adisplay 3704, operation switches 3705, an antenna 3706 and a sensorportion 3707. The present invention can be used as the sensor portion3707.

[0240] The present invention enables enlarging of the amplitude of theoutput while preventing the writing-in time of the output electricpotential of the source follower circuit from becoming long. Further, atthe same time, the present invention can widen the operating region inwhich the input/output relationship of the source follower circuit islinear. Consequently, an area sensor having a high image quality isrealized.

What is claimed is:
 1. A semiconductor device comprising: an amplifyingtransistor; a biasing transistor; an amplifying side power source line;a biasing side power source line; a bias signal line; an electricdischarging transistor; and an electric discharging power source line,wherein a drain terminal of the amplifying transistor is connected tothe amplifying side power source line, a source terminal of the biasingtransistor is connected to the biasing side power source line, a sourceterminal of the amplifying transistor is connected to a drain terminalof the biasing transistor, a gate terminal of the biasing transistor isconnected to the bias signal line, a gate terminal of the amplifyingtransistor serves as an input terminal, and a source terminal of theamplifying transistor serves as an output terminal, and wherein one ofthe output terminal and the electric discharging power source line isconnected to a source terminal of the electric discharging transistorwhile the other thereof is connected to a drain terminal of the electricdischarging transistor.
 2. A device according to claim 1 furthercomprising a load capacitance wherein one terminal of the loadcapacitance is connected to the output terminal, and the other terminalof the load capacitance is connected to a load capacitance power sourceline.
 3. A device according to claim 1 , wherein the electricdischarging power source line is connected to the biasing side powersource line.
 4. A device according to claim 1 further comprising atleast one selecting switch for controlling an electric current flowingto the output terminal from the amplifying side power source line orfrom the biasing side power source line.
 5. A device according to claim1 wherein an absolute value of a voltage between a gate and a source ofthe biasing transistor is equivalent to a minimum value of an absolutevalue of a voltage between a gate and a source that is necessary formaking the biasing transistor into a conductive state.
 6. A deviceaccording to claim 1 , wherein a photoelectric conversion element isconnected to the input terminal.
 7. A device according to claim 1 ,wherein a signal generated by a photoelectric conversion element is fedto the input terminal.
 8. A device according to claim 1 , wherein whenthe semiconductor device has a plurality of biasing transistors, anabsolute value of a voltage between a gate and a source of the pluralityof biasing transistors is equivalent to a minimum value of an absolutevalue of a voltage between a gate and a source that is necessary formaking the entire plurality of biasing transistors into a conductivestate.
 9. A device according to claim 1 , wherein the amplifyingtransistor, the biasing transistor, and the electric dischargingtransistor are transistors having the same polarity.
 10. A scanner,which uses the semiconductor device according to claim 1 .
 11. A digitalstill camera, which uses the semiconductor device according to claim 1 .12. An X-ray camera, which uses the semiconductor device according toclaim 1 .
 13. A portable information terminal, which uses thesemiconductor device according to claim 1 .
 14. A computer, which usesthe semiconductor device according to claim 1 .
 15. A device accordingto claim 2 , wherein at least 2 lines from among the electricdischarging power source line, the load capacitance power source line,and the biasing side power source line are connected together.
 16. Adevice according to claim 2 , wherein the load capacitance power sourceline is connected to the amplifying side power source line.
 17. A deviceaccording to claim 2 further comprising at least one selecting switchfor controlling an electric current flowing to the load capacitance orthe output terminal from the amplifying side power source line or fromthe biasing side power source line.
 18. A device according to claim 17 ,wherein the selecting switch has at least one of an N channel transistoror a P channel transistor.
 19. A device according to claim 6 , whereinthe photoelectric conversion element is either an X-ray sensor or aninfrared sensor.
 20. A device according to claim 6 , wherein thephotoelectric conversion element is any one of a photo diode, a Schottkydiode, an avalanche diode, or a photo conductor.
 21. A device accordingto claim 20 , wherein the photo diode is one of a type incorporating aPN type, a PIN type, or an NPN embedded type.
 22. A device according toclaims 6 further comprising a resetting transistor, and a sourceterminal or a drain terminal of the resetting transistor is connected tothe photoelectric conversion element.
 23. A semiconductor devicecomprising: an amplifying transistor; a biasing transistor; anamplifying side power source line; a biasing side power source line; asignal generating device; and a bias signal line, wherein a drainterminal of the amplifying transistor is connected to the amplifyingside power source line, a source terminal of the biasing transistor isconnected to the biasing side power source line, a source terminal ofthe amplifying transistor is connected to a drain terminal of thebiasing transistor, a gate terminal of the biasing transistor isconnected to the bias signal line, a gate terminal of the amplifyingtransistor serves as an input terminal, and a source terminal of theamplifying transistor serves as an output terminal, and wherein thesignal generating device is connected to the bias signal line forperforming the operation of making the electric potential of the biasingside power source line close to the electric potential of the amplifyingside power source line.
 24. A device according to claim 23 furthercomprising a load capacitance wherein one terminal of the loadcapacitance is connected to the output terminal, and the other terminalof the load capacitance is connected to a load capacitance power sourceline.
 25. A device according to claim 23 further comprising at least oneselecting switch for controlling an electric current flowing to theoutput terminal from the amplifying side power source line or from thebiasing side power source line.
 26. A device according to claim 23wherein an absolute value of a voltage between a gate and a source ofthe biasing transistor is equivalent to a minimum value of an absolutevalue of a voltage between a gate and a source that is necessary formaking the biasing transistor into a conductive state.
 27. A deviceaccording to claim 23 , wherein a photoelectric conversion element isconnected to the input terminal.
 28. A device according to claim 23 ,wherein a signal generated by a photoelectric conversion element is fedto the input terminal.
 29. A device according to claim 23 , wherein whenthe semiconductor device has a plurality of biasing transistors, anabsolute value of a voltage between a gate and a source of the pluralityof biasing transistors is equivalent to a minimum value of an absolutevalue of a voltage between a gate and a source that is necessary formaking the entire plurality of biasing transistors into a conductivestate.
 30. A scanner, which uses the semiconductor device according toclaim 23 .
 31. A digital still camera, which uses the semiconductordevice according to claim 23 .
 32. An X-ray camera, which uses thesemiconductor device according to claim 23 .
 33. A portable informationterminal, which uses the semiconductor device according to claim 23 .34. A computer, which uses the semiconductor device according to claim23 .
 35. A driving method of a semiconductor device having an amplifyingtransistor, a biasing transistor, an amplifying side power source line,a biasing side power source line, and a bias signal line, wherein adrain terminal of the amplifying transistor is connected to theamplifying side power source line, a source terminal of the biasingtransistor is connected to the biasing side power source line, a sourceterminal of the amplifying transistor is connected to a drain terminalof the biasing transistor, wherein a gate terminal of the biasingtransistor is connected to the bias signal line, a gate terminal of theamplifying transistor serves as an input terminal, and a source terminalof the amplifying transistor serves as an output terminal, and whereinthe driving method outputs a signal after performing a pre-discharge.36. A method according to claim 35 further comprising a load capacitancewherein one terminal of the load capacitance is connected to the outputterminal, and the other terminal of the load capacitance is connected toa load capacitance power source line.
 37. A method according to claim 35, wherein the semiconductor device has at least one selecting switch forcontrolling an electric current flowing to the output terminal from theamplifying side power source line or from the biasing side power sourceline.
 38. A method according to claim 35 , wherein an absolute value ofa voltage between a gate and a source of the biasing transistor isequivalent to a minimum value of an absolute value of a voltage betweena gate and a source that is necessary for making the biasing transistorinto a conductive state.
 39. A method according to claim 35 furthercomprising a photoelectric conversion element connected to the inputterminal.
 40. A method according to claim 35 , wherein a signalgenerated by a photoelectric conversion element is fed to the inputterminal.
 41. A method according to claim 35 , wherein when thesemiconductor device has a plurality of biasing transistors, an absolutevalue of a voltage between a gate and a source of the plurality ofbiasing transistor is equivalent to a minimum value of an absolute valueof a voltage between a gate and a source that is necessary for makingthe entire plurality of biasing transistors into a conductive state. 42.A method according to claim 36 , wherein at least 2 lines from among theelectric discharging power source line, the load capacitance powersource line, and the biasing side power source line are to be connectedtogether.
 43. A method according to claim 36 , wherein the loadcapacitance power source line is connected to the amplifying side powersource line.
 44. A method according claims 36, wherein the semiconductordevice has at least one selecting switch for controlling an electriccurrent flowing to the load capacitance or the output terminal from theamplifying side power source line or from the biasing side power sourceline.
 45. A method according to claim 44 , wherein the selecting switchhas at least one of an N channel transistor or a P channel transistor.46. A method according to claim 39 , wherein the photoelectricconversion element is either an X-ray sensor or an infrared sensor. 47.A method according to claim 39 , wherein the photoelectric conversionelement is any one of a photo diode, a Schottky diode, an avalanchediode, or a photo conductor.
 48. A method according to claim 47 ,wherein the photo diode is any one of a type incorporating a PN type, aPIN type, or an NPN embedded type.
 49. A method according to claim 39 ,wherein the semiconductor device has a resetting transistor, and theresetting transistor resets the photoelectric conversion element.
 50. Adriving method of a semiconductor device having an amplifyingtransistor, a biasing transistor, an amplifying side power source line,a biasing side power source line, and a bias signal line, wherein adrain terminal of the amplifying transistor is connected to theamplifying side power source line, a source terminal of the biasingtransistor is connected to the biasing side power source line, a sourceterminal of the amplifying transistor is connected to a drain terminalof the biasing transistor, a gate terminal of the biasing transistor isconnected to the bias signal line, a gate terminal of the amplifyingtransistor serves as an input terminal, and a source terminal of theamplifying transistor serves as an output terminal, and wherein thedriving method outputs a signal after performing a pre-discharge bymaking an electric potential of the biasing side power source line closeto an electric potential of the amplifying side power source line.
 51. Amethod according to claim 50 further comprising a load capacitancewherein one terminal of the load capacitance is connected to the outputterminal, and the other terminal of the load capacitance is connected toa load capacitance power source line.
 52. A method according to claim 50, wherein the semiconductor device has at least one selecting switch forcontrolling an electric current flowing to the output terminal from theamplifying side power source line or from the biasing side power sourceline.
 53. A method according to claim 50 , wherein an absolute value ofa voltage between a gate and a source of the biasing transistor isequivalent to a minimum value of an absolute value of a voltage betweena gate and a source that is necessary for making the biasing transistorinto a conductive state.
 54. A method according to claim 50 furthercomprising a photoelectric conversion element connected to the inputterminal.
 55. A method according to claim 50 , wherein a signalgenerated by a photoelectric conversion element is fed to the inputterminal.
 56. A method according to claim 50 , wherein when thesemiconductor device has a plurality of biasing transistors, an absolutevalue of a voltage between a gate and a source of the plurality ofbiasing transistor is equivalent to a minimum value of an absolute valueof a voltage between a gate and a source that is necessary for makingthe entire plurality of biasing transistors into a conductive state. 57.A driving method of a semiconductor device having an amplifyingtransistor, a biasing transistor, an amplifying side power source line,a biasing side power source line, and a bias signal line, an electricdischarging transistor, and an electric discharging power source line,wherein a drain terminal of the amplifying transistor is connected tothe amplifying side power source line, a source terminal of the biasingtransistor is connected to the biasing side power source line, a sourceterminal of the amplifying transistor is connected to a drain terminalof the biasing transistor, a gate terminal of the biasing transistor isconnected to the bias signal line, a gate terminal of the amplifyingtransistor serves as an input terminal, a source terminal of theamplifying transistor serves as an output terminal, one of the outputterminal and the electric discharging power source line is connected toa source terminal of the electric discharging transistor while the otherthereof is connected to a drain terminal of the electric dischargingtransistor, and wherein the driving method outputs a signal afterperforming a pre-discharge by making the electric discharging transistorinto a conductive state.
 58. A method according to claim 57 , wherein avalue of an electric potential of the electric discharging power sourceline takes a value that is between an electric potential of the biassignal line and an electric potential of the biasing side power sourceline.
 59. A method according to claim 57 further comprising a loadcapacitance wherein one terminal of the load capacitance is connected tothe output terminal, and the other terminal of the load capacitance isconnected to a load capacitance power source line.
 60. A methodaccording to claim 57 , wherein the electric discharging power sourceline and the biasing side power source line are to be connectedtogether.
 61. A method according to claim 57 , wherein the semiconductordevice has at least one selecting switch for controlling an electriccurrent flowing to the output terminal from the amplifying side powersource line or from the biasing side power source line.
 62. A methodaccording to claim 57 , wherein an absolute value of a voltage between agate and a source of the biasing transistor is equivalent to a minimumvalue of an absolute value of a voltage between a gate and a source thatis necessary for making the biasing transistor into a conductive state.63. A method according to claim 57 further comprising a photoelectricconversion element connected to the input terminal.
 64. A methodaccording to claim 57 , wherein a signal generated by a photoelectricconversion element is fed to the input terminal.
 65. A method accordingto claim 57 , wherein when the semiconductor device has a plurality ofbiasing transistors, an absolute value of a voltage between a gate and asource of the plurality of biasing transistor is equivalent to a minimumvalue of an absolute value of a voltage between a gate and a source thatis necessary for making the entire plurality of biasing transistors intoa conductive state.
 66. A method according to claims 57, wherein theamplifying transistor, the biasing transistor, and the electricdischarging transistor are transistors having the same polarity.